Embedded PHY (EPHY) IP core for FPGA

Patent metadata

Field	Value
Publication number	US-11675008-B2
Application number	US-202016805244-A
Country	US
Kind code	B2
Filing date	Feb 28, 2020
Priority date	Feb 28, 2020
Publication date	Jun 13, 2023
Grant date	Jun 13, 2023

Abstract

The present disclosure generally relates to an embedded physical layer (EPHY) for a field programmable gate array (FPGA). The EPHY for the FPGA is for a testing device that can receive and transmit in both the high speed PHYs, as well as low speed PHYs, such as MIPI PHYs (MPHYs), to meet universal flash storage (UFS) specifications. The testing device with the EPHY for the FPGA provides flexibility to support any specification updates without the need of application specific (ASIC) production cycles.

First claim

What is claimed is:

1. An embedded physical layer (EPHY), comprising:
a glue hardware portion; and
a logic portion for communicating with a device under test (DUT) through the glue hardware portion, wherein the logic portion comprises:
a plurality of transmission blocks that each includes:
a transmission remote monitor and maintenance interface (RMMI) multiplexer (MUX) and wrapper;
a first low speed logic block of a first speed; and
a first high speed logic block of a second speed, wherein the second speed is greater than the first speed, wherein the transmission RMMI MUX and wrapper is configured to input a data signal and a clock signal to the first low speed logic block, wherein the transmission RMMI MUX and wrapper is configured to input a data signal and a clock signal to the first high speed logic block, wherein the first low speed logic block and first high speed logic block are configured to output data to the glue hardware portion; and

a plurality of receive blocks that each includes:
a receive RMMI MUX and wrapper;
a second low speed logic block of a third speed; and
a second high speed logic block of a fourth speed, wherein the fourth speed is greater than the third speed, wherein the receive RMMI MUX and wrapper is configured to receive a data signal and a clock signal from the second low speed logic block, wherein the receive RMMI MUX and wrapper is configured to receive a data signal and a clock signal from the second high speed logic block, wherein the second low speed logic block and second high speed logic block are configured to receive data from the glue hardware portion.

2. The EPHY of claim 1 , wherein each first low speed logic block comprises a delay tap configured to receive an input from the transmission RMMI MUX and wrapper.

3. The EPHY of claim 2 , wherein each first low speed logic block includes a pulse width modulator and a first low speed logic block MUX.

4. The EPHY of claim 3 , wherein the transmission RMMI MUX and wrapper outputs a data signal to the delay tap and the first low speed logic block MUX, then is the data signal, from the first low speed logic block MUX, is input to the pulse width modulator.

5. The EPHY of claim 4 , wherein an output of the delay tap feeds to the first low speed logic MUX.

6. The EPHY of claim 5 , wherein an output of the first low speed logic MUX is fed to the pulse width modulator of the first low speed logic block.

7. The EPHY of claim 6 , wherein an output of the pulse width modulator of the first low speed logic block is fed to the glue hardware portion.

8. The EPHY of claim 1 , wherein each second low speed logic block includes a pulse width modulator and a second low speed logic block MUX.

9. The EPHY of claim 8 , wherein each pulse width modulator of the second low speed logic block is configured to receive a signal from the glue hardware portion.

10. The EPHY of claim 9 , wherein each second low speed logic block comprises a delay tap configured to receive an input from the pulse width modulator of the second low speed logic block.

11. The EPHY of claim 10 , wherein each low speed logic block delay tap is configured to output a signal to the receive RMMI MUX and wrapper.

12. The EPHY of claim 11 , wherein the pulse width modulator of the second low speed logic block is configured to receive the signal from the glue hardware portion through a MUX.

13. The EPHY of claim 1 , wherein a number of the plurality of transmission blocks is equal to a number of the plurality of receive blocks.

14. The EPHY of claim 1 , further comprising a plurality of MUXs coupled to each transmission block.

15. The EPHY of claim 14 , wherein the plurality of MUXs is coupled to the transmission RMMI MUX and wrapper for each transmission block.

16. The EPHY of claim 1 , further comprising a controller coupled to each transmission block and each receive block.

17. The EPHY of claim 16 , further comprising a clock generator coupled to the controller.

18. The EPHY of claim 1 , wherein each receive block includes a receive block fine state machine (FSM) and each transmission block includes a transmission block FSM.

19. The EPHY of claim 18 , wherein each receive block FSM is coupled to a corresponding transmission block FSM.

20. The EPHY of claim 19 , wherein the glue hardware portion includes differential amplifiers.

Assignees

• Western Digital Tech Inc

Inventors

• Ganon Doron
• Lerner Eitan

Classifications

• G06F1/04

  Generating or distributing clock signals or signals derived directly therefrom · CPC title

• G06F30/347 Primary

  Physical level, e.g. placement or routing · CPC title

• G01R31/31917

  Stimuli generation or application of test patterns to the device under test [DUT] · CPC title

• G01R31/31908

  Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns · CPC title

• G01R31/318335 Primary

  Test pattern compression or decompression (compression or decompression of scan patterns G01R31/318547; compression or decompression hardware G01R31/31921) · CPC title