Method and apparatus for detecting defective logic devices

Patent metadata

Field	Value
Publication number	US-11675004-B2
Application number	US-202016989726-A
Country	US
Kind code	B2
Filing date	Aug 10, 2020
Priority date	May 14, 2020
Publication date	Jun 13, 2023
Grant date	Jun 13, 2023

Abstract

An apparatus for testing a device under test (DUT) is provided. The apparatus includes a power supply device and a data generating device. The power supply device is configured to provide a first voltage and a second voltage to the DUT. The data generating device is configured to provide first data to the DUT. The power supply device is configured to provide the first voltage to the DUT in a first time duration. The data generating device is configured to provide the first data to the DUT in the first time duration. The power supply device is configured to provide the second voltage to the DUT in a second time duration after the first time duration. The second voltage is different from the first voltage.

First claim

What is claimed is:

1. An apparatus for testing a device under test (DUT), comprising:
a power supply device configured to provide a first voltage and a second voltage to the DUT;
a clock device; and
a data generating device configured to provide first data to the DUT, wherein
the power supply device is configured to provide the first voltage to the DUT in a first time duration;
the data generating device is configured to provide the first data to the DUT in the first time duration;
the power supply device is configured to provide the second voltage to the DUT in a second time duration after the first time duration;
the clock device is configured to provide a clock signal to the DUT in the first time duration and stop providing the clock signal to the DUT in the second time duration; and
the second voltage is different from the first voltage, wherein the DUT comprises a first number of information storage units connected in series, and the first data comprises a second number of bits, wherein the second number is identical to the first number.

2. The apparatus of claim 1 , wherein the power supply device is further configured to provide the first voltage to the DUT in a third time duration after the second time duration.

3. The apparatus of claim 1 , wherein the data generating device is further configured to provide second data to the DUT in a third time duration after the second time duration.

4. The apparatus of claim 1 , wherein a ratio of the second voltage to the first voltage ranges from 80% to 20%.

5. The apparatus of claim 1 , wherein the second time duration is greater than 100 ms.

6. A method for testing a logic device, comprising:
providing a first voltage to the logic device in a first time duration;
providing first data to the logic device in the first time duration;
providing a clock signal to the logic device in the first time duration;
providing a second voltage different from the first voltage to the logic device in a second time duration after the first time duration;
stopping providing the clock signal to the logic device in the second time duration;
providing the first voltage to the logic device in a third time duration after the second time duration;
providing second data to the logic device in the third time duration; and
comparing the first data with first output data outputted by the logic device, the first output data is generated by the logic device in response to the second data provided in the third time duration.

7. The method of claim 6 , wherein a ratio between the second voltage to the first voltage ranges from 80% to 20%.

8. The method of claim 6 , wherein the second time duration is greater than 100 ms.

9. The method of claim 6 , further comprising:
providing third data to the logic device in a fourth time duration after the third time duration;
providing the first voltage to the logic device in the fourth time duration; and
providing the second voltage to the logic device in a fifth time duration after the fourth time duration, wherein the third data is different from the first data.

10. The method of claim 9 , further comprising:
providing the first voltage to the logic device in a sixth time duration after the fifth time duration;
providing the second data to the logic device in the sixth time duration; and
comparing the third data with second output data outputted by the logic device, the second output data is generated by the logic device in response to the second data provided in the sixth time duration.

11. A method for testing a semiconductor device having a first number of information storage units connected in series, comprising:
providing a first voltage and first data having a second number of bits to the semiconductor device;
providing a second voltage different from the first voltage to the semiconductor device for a first time duration;
stopping providing a clock signal to the semiconductor device in the first time duration;
providing the first voltage and second data to the semiconductor device; and
comparing first output data outputted by the semiconductor device with the first data wherein the second number is identical to the first number.

12. The method of claim 11 , wherein a ratio between the second voltage to the first voltage ranges from 80% to 20%.

13. The method of claim 11 , wherein the first time duration is greater than 100 ms.

14. The method of claim 11 , further comprising:
providing the first voltage and third data different from the first data to the semiconductor device;
providing the second voltage to the semiconductor device for the first time duration;
providing the first voltage and the second data to the semiconductor device; and
comparing second output data outputted by the semiconductor device with the third data.

15. The apparatus of claim 3 , wherein:
the data generating device is configured to provide third data different from the first data to the logic device in a fourth time duration after the third time duration;
the power supply device is configured to provide the first voltage to the logic device in the fourth time duration, and provide the second voltage to the logic device in a fifth time duration after the fourth time duration.

16. The apparatus of claim 15 , wherein the clock device is configured to provide the clock signal to the DUT in the fourth time duration and stop providing the clock signal to the DUT in the fifth time duration.

17. The method of claim 9 , further comprising: providing the clock signal to the logic device in the fourth time duration and stop providing the clock signal to the logic device in the fifth time duration.

18. The method of claim 6 , wherein the logic device includes a first number of information storage units connected in series, and the first data includes a second number of bits, wherein the second number is identical to the first number.

19. The apparatus of claim 3 , wherein the data generating device is further configured to generate first output data in response to the second data provided in the third time duration.

20. The apparatus of claim 19 , wherein the first output data comprises a third number of bits, wherein the third number is identical to the first number.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wu Chi-Che
• Hung Tsung-Yang
• Wang Ming-Yih
• Guo Jia-Ming

Classifications

• G01R31/31721 Primary

  Power aspects, e.g. power supplies for test circuits, power saving during test (for scan test G01R31/318575) · CPC title

• G01R31/3177 Primary

  Testing of logic operation, e.g. by logic analysers · CPC title

• G01R31/3008

  Quiescent current [IDDQ] test or leakage current test · CPC title

• G01R31/31924

  Voltage or current aspects, e.g. driver, receiver · CPC title

• G01R31/31725

  Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937) · CPC title