Dead time control in a switching cell

Patent metadata

Field	Value
Publication number	US-11671005-B2
Application number	US-202016950707-A
Country	US
Kind code	B2
Filing date	Nov 17, 2020
Priority date	Nov 25, 2019
Publication date	Jun 6, 2023
Grant date	Jun 6, 2023

Abstract

A method of controlling first and second switches of a switching cell, including measuring a current flowing through the first switch when the first switch is controlled to the off state, and setting a switching dead time according to the measurement.

First claim

What is claimed is:

1. A switching cell comprising first and second switches series-coupled, the first switch comprising a diode, coupling terminals of the first switch and oriented to conduct a current supplied or received by the switching cell when the first and second switches are simultaneously in the off state, the switching cell comprising a device configured to implement a method comprising measuring a current flowing through the first switch when the first switch is controlled to the off state, and setting a switching dead time according to the measurement,
wherein the setting comprises determining a first value representative of an integral of a second value resulting from the measurement during an integration period,
and wherein said setting comprises searching for a third value of the switching dead time for which the first value representative of the integral exhibits an extremum,
wherein the switching cell comprises a sensor configured to measure the current flowing through the first switch,
and wherein said device comprises:
a comparator circuit and a link between an input of the comparator circuit and said sensor, another input of the comparator circuit being coupled to a first node of application of a fixed potential;
a monostable circuit having a trigger input coupled to an output of the comparator circuit;
a multiplexer controlled by the monostable circuit and having an input coupled to said sensor; and
an integrator circuit having an input coupled to an output of the multiplexer, the integrator circuit preferably comprising a resistor and a capacitor in series between said input of the integrator circuit and the first node or another node of application of a fixed potential.

2. The switching cell according to claim 1 , wherein said device is configured to perform the measurement when the second switch is controlled to the on state.

3. The switching cell according to claim 1 , wherein a duration of the integration period is predefined and/or in the range from 0.1% to 50% of a switching cycle time, and/or greater than or equal to a duration between two successive zero crossings of the current flowing through the first switch.

4. The switching cell according to claim 1 , wherein the integration period starts at a time when said second value resulting from the measurement is representative of a zero value of the current flowing through the first switch.

5. The switching cell according to claim 1 , wherein said sensor comprises a magnetic-type sensor.

6. The switching cell according to claim 1 , comprising a third switch coupling output terminals of said sensor.

7. The switching cell according to claim 1 , wherein:
said link comprises another multiplexer having an input coupled to said sensor and an output coupled to said input of the comparator circuit, said other multiplexer having another input coupled to the first node or to a second node of application of a fixed potential; and
another monostable circuit has a trigger input coupled to the output of said monostable circuit and controls said other multiplexer.

8. A switched-mode converter comprising at least one switching cell according to claim 1 .

9. The switching cell according to claim 5 , wherein the magnetic-type sensor is a transformer.

10. The switching cell according to claim 6 , wherein the third switch is controlled by a same control signal as the first switch.

Assignees

• Commissariat Energie Atomique

Inventors

• Lefevre Guillaume
• Piquet-Boisson Guillaume

Classifications

• H02M1/0048

  Circuits or arrangements for reducing losses (using snubbers H02M1/34) · CPC title

• H02M1/38 Primary

  Means for preventing simultaneous conduction of switches · CPC title

• H02M1/083

  for the ignition at the zero crossing of the voltage or the current · CPC title

• H02M1/12

  Arrangements for reducing harmonics from AC input or output · CPC title

• Y02B70/10

  Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title