PCM metal shielding for wafer testing

Patent metadata

Field	Value
Publication number	US-11670555-B2
Application number	US-202017127884-A
Country	US
Kind code	B2
Filing date	Dec 18, 2020
Priority date	Dec 18, 2020
Publication date	Jun 6, 2023
Grant date	Jun 6, 2023

Abstract

Method and devices to reduce integrated circuit fabrication process yield loss due to undesired interactions between PCMs and the wafer test probes during wafer sorting tests are disclosed. The described methods entail the use of a properly patterned metal layer on the PCM dies adjacent to the product dies under test. Such patterned metal layers shield traces of the wafer probes from the circuits of the PCM dies. Various exemplary metal layer patterns are also presented.

First claim

The invention claimed is:

1. A wafer comprising a plurality of dies including a first die and a second die adjacent to or in proximity of the first die, wherein:
the first die comprises a device under test configured to receive radio frequency (RF) test signals through a wafer probe for wafer testing, the wafer probe including traces to conduct the RF test signals; and
the second die comprises test pads, circuits and a patterned metal layer patterned to electrically shield the traces conducting the RF test signals applied to the first die from the circuits in the second die, the test pads being electrically isolated from the patterned metal layer.

2. The wafer of claim 1 , wherein the patterned metal layer comprises openings to leave the test pads accessible for testing.

3. The wafer of claim 2 , wherein the patterned metal layer has a mesh pattern, and wherein the openings of the patterned metal layer are smaller than one quarter of a wavelength of the RF test signals to be applied to the first die.

4. The wafer of claim 1 , wherein the patterned metal layer is a topmost metal layer of the second die.

5. The wafer of claim 1 , wherein the patterned metal layer is a non-topmost metal layer of the second die.

6. The wafer of claim 1 , wherein the patterned metal layer fills more than 50% of an area of the second die.

7. The wafer of claim 6 , wherein the patterned metal layer fills more than 80% of the area of the second die.

8. The wafer of claim 7 , wherein the patterned metal layer fills more than 95% of the area of the second die.

9. The wafer of claim 1 , wherein the circuits comprise active circuits.

10. The wafer of claim 1 , wherein the patterned metal layer has a first region filling a first portion of an area of the second die, and a second region having a mesh pattern.

11. The wafer of claim 1 , further comprising a substrate and a die with a seal ring, wherein the patterned metal layer is tied to the seal ring.

12. The wafer of claim 1 , wherein the test pads of the second die are connected to process control monitors.

13. The wafer of claim 1 , wherein the patterned metal layer has a thickness ranging from 50 nm to 3 um.

14. The wafer of claim 1 , wherein the patterned metal layer is made of a material selected from the group consisting of aluminum, nickel, chromium, gold, germanium, copper, silver, titanium, tungsten, platinum, and tantalum.

15. A wafer testing method comprising:
providing a wafer comprising a plurality of dies including a first die and a second die being adjacent to or in proximity of the first die, the second die comprising circuitry, test pads and a patterned metal layer patterned to leave the test pads accessible for testing through openings in the patterned metal layer, the test pads being electrically isolated from the patterned metal layer;
providing a wafer probe comprising traces; and
applying radio frequency (RF) test signals to the first die through the traces of the wafer probe while shielding the traces from the circuitry of the second die by the patterned metal layer of the second die.

16. The wafer testing method of claim 15 , wherein the patterned metal layer has a mesh pattern with openings smaller than one quarter of a wavelength of the RF test signals.

17. The wafer of claim 15 , wherein the patterned metal layer fills more than 50% of the area of the second die.

18. The wafer of claim 17 , wherein the patterned metal layer fills more than 80% of the area of the second die.

19. The wafer of claim 18 , wherein the patterned metal layer fills more than 95% of the area of the second die.

20. The wafer testing method of claim 15 , wherein the patterned metal layer has a first region filling a first portion of an area of the second die, and a second region having a mesh pattern.

21. The wafer testing method of claim 15 , wherein the second die further comprises process control monitors connected to the test pads.

22. The wafer testing method of claim 15 , wherein the patterned metal layer has a thickness ranging from 50 nm to 3 um.

23. The wafer testing method of claim 15 , wherein the patterned metal layer is made of a material selected from the group consisting of aluminum, nickel, chromium, gold, germanium, copper, silver, titanium, tungsten, platinum, and tantalum.

24. The wafer testing method of claim 15 , wherein the circuitry comprises active circuits.

Assignees

• Psemi Corp

Inventors

• Hamilton Jacob
• Kononova Tran
• Kothari Jay
• Allison Matt
• Nguyen Kim T
• Shapiro Eric S

Classifications

• H10W42/121

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• H10W42/00

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10W20/423

  Shielding layers · CPC title

• H10P74/273 Primary

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10P74/277 Primary

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title