Display element, display device, and electronic device

Patent metadata

Field	Value
Publication number	US-11670241-B2
Application number	US-202217859751-A
Country	US
Kind code	B2
Filing date	Jul 7, 2022
Priority date	Sep 22, 2017
Publication date	Jun 6, 2023
Grant date	Jun 6, 2023

Abstract

A display element includes a light-emitting unit of a current drive type, and a drive unit that drives the light-emitting unit, in which the drive unit includes a capacitance unit, a drive transistor that causes a current corresponding to a voltage held by the capacitance unit to flow through the light-emitting unit, and a write transistor that writes a signal voltage to the capacitance unit, the drive transistor and the write transistor are formed in a state of being separated by an element isolation region, on a semiconductor substrate, and a capacitance generated in a portion where the drive transistor and the write transistor face each other through the element isolation region functions as at least a part of the capacitance unit.

First claim

The invention claimed is:

1. A display device comprising:
a plurality of data lines extending in a first direction;
a plurality of control lines extending in a second direction different from the first direction;
a plurality of pixel circuits arranged in a matrix;
wherein each of the plurality of pixel circuits includes:
a light emitting element,
a first transistor, a second transistor and a third transistor, and
a capacitor configured to store data voltage supplied from a corresponding one of the plurality of data lines,
wherein a channel length direction of each of the first transistor, the second transistor and the third transistor extends in the first direction,
at least a portion of a channel region of the second transistor is parallel to a channel region of the third transistor in the second direction,
a portion of an element isolation region of a semiconductor substrate is arranged between one of a source or a drain of the first transistor and one of a source or a drain of the third transistor, and
each of a channel region of the first transistor and the channel region of the second transistor is part of island-shaped semiconductor layer on the semiconductor substrate in a plan view.

2. The display device according to claim 1 , the one of the source or the drain of the first transistor is directly electrically connected to one of a source or a drain of the second transistor.

3. The display device according to claim 1 , wherein one of the plurality of control lines corresponding to the second transistor is arranged to intersect the channel region of the third transistor.

4. The display device according to claim 1 , wherein a first electrode of the capacitor is directly electrically connected to the one of the source or the drain of the first transistor.

5. The display device according to claim 1 , wherein a second electrode of the capacitor is directly electrically connected to a gate of the first transistor.

6. The display device according to claim 1 , wherein the third transistor is configured to control writing of the data voltage supplied from the corresponding one of the plurality of data lines into the capacitor.

7. The display device according to claim 1 , wherein the first transistor and the second transistor are connected in series.

8. The display device according to claim 1 , wherein the light emitting element, the first transistor and the second transistor are connected in series.

9. The display device according to claim 1 , wherein a channel region of the third transistor is a part of the island-shaped semiconductor layer structurally separated from a semiconductor layer of the first transistor and a semiconductor layer of the second transistor.

10. A display device comprising:
a plurality of data lines extending in a first direction;
a plurality of control lines extending in a second direction different from the first direction;
a plurality of pixel circuits arranged in a matrix;
wherein each of the plurality of pixel circuits includes:
a light emitting element,
a first transistor, a second transistor and a third transistor, and
a capacitor configured to store data voltage supplied from a corresponding one of the plurality of data lines,
wherein a channel length direction of each of the first transistor, the second transistor and the third transistor extends in the first direction,
at least a portion of a channel region of the second transistor is parallel to a channel region of the third transistor in the second direction,
a portion of an element isolation region of a semiconductor substrate is arranged between one of a source or a drain of the first transistor and one of a source or a drain of the third transistor, and
a semiconductor layer of the first transistor and a semiconductor layer of the second transistor are not structurally separated by the element isolation region.

11. The display device according to claim 10 , the one of the source or the drain of the first transistor is directly electrically connected to one of a source or a drain of the second transistor.

12. The display device according to claim 10 , wherein one of the plurality of control lines corresponding to the second transistor is arranged to intersect the channel region of the third transistor.

13. The display device according to claim 10 , wherein a first electrode of the capacitor is directly electrically connected to the one of the source or the drain of the first transistor.

14. The display device according to claim 10 , wherein a second electrode of the capacitor is directly electrically connected to a gate of the first transistor.

15. The display device according to claim 10 , wherein the third transistor is configured to control writing of data voltage supplied from the corresponding one of the plurality of data lines into the capacitor.

16. The display device according to claim 10 , wherein the first transistor and the second transistor are connected in series.

17. The display device according to claim 10 , wherein the light emitting element, the first transistor and the second transistor are connected in series.

18. The display device according to claim 10 , wherein a channel region of the third transistor is a part of the island-shaped semiconductor layer structurally separated from a semiconductor layer of the first transistor and a semiconductor layer of the second transistor.

Assignees

• Sony Group Corp

Inventors

• Kimura Kei

Classifications

• H10D84/813

  Combinations of field-effect devices and capacitor only · CPC title

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G2300/0876

  Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes · CPC title

• G09G2300/043

  Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title