Display panel and display apparatus

Patent metadata

Field	Value
Publication number	US-11669133-B2
Application number	US-202117546737-A
Country	US
Kind code	B2
Filing date	Dec 9, 2021
Priority date	Sep 12, 2019
Publication date	Jun 6, 2023
Grant date	Jun 6, 2023

Abstract

A display panel including a first display area, a second display area and a third display area. The second display area surrounds at least a part of the first display area and is located between the first display area and the third display area; the second display area includes a plurality of first groups of driving transistors and a plurality of second groups of driving transistors, the first groups of driving transistors include driving transistors for driving pixel units of the first display area, the second groups of driving transistors include driving transistors for driving pixel units of the second display area. The second groups of driving transistors and the first groups of driving transistors are alternately arranged, and a number and relative positions of the second groups of driving transistors adjacent to each first group of driving transistors are the same.

First claim

What is claimed is:

1. A display panel, comprising:
a first display area;
a second display area; and
a third display area, wherein the second display area surrounds at least a part of the first display area and is located between the first display area and the third display area, a light transmittance of the first display area is higher than a light transmittance of the second display area and a light transmittance of the third display area;
a plurality of pixel units, located in the first display area, the second display area and the third display area and having a plurality of sub-pixels;
a plurality of first driving transistor groups, disposed in the second display area and having a plurality of driving transistors for driving the pixel units disposed in the first display area; and
a plurality of second driving transistor groups, disposed in the second display area and having a plurality of driving transistors for driving the pixel units disposed in the second display area;
the second driving transistor groups and the first driving transistor groups are alternately arranged; and wherein M 1 sub-pixels emitting a same color disposed in the second display area are connected in series via a connecting line and connected to a same driving transistor disposed in the second display area; wherein M 1 is an integer greater than or equal to 2;
the connecting line is overlapped with the driving transistor disposed in the second display area along a stacking direction.

2. The display panel of claim 1 , further comprising a plurality of minimum repeating units consisting of adjacent two groups of the first driving transistor groups and the second driving transistor groups with the corresponding pixel units, wherein the minimum repeating units are arranged in a periodicity.

3. The display panel of claim 1 , wherein the connecting line disposed in the second display area is connected with an anode of the corresponding sub-pixel disposed in the second display area, and the connecting line has a same material as said anode and is formed in a same process with said anode.

4. The display panel of claim 3 , wherein a plurality of gate electrodes of the driving transistors of the first driving transistor groups have a plurality of overlaps with the connecting lines in the stacking direction and a plurality of first parasitic capacitances in the overlaps, a plurality of gate electrodes of the driving transistors of the second driving transistor groups have a plurality of overlaps with the connecting lines in the stacking direction and a plurality of second parasitic capacitances in the overlaps, and the first parasitic capacitances are same as the second parasitic capacitances.

5. The display panel of claim 4 , wherein a via of the gate electrode of each driving transistor in the first driving transistor groups has a first projection on a corresponding pixel unit, and the positions of the first projections are the same with each other;
a via of the gate electrode of each driving transistor in the second driving transistor groups has a second projection on a corresponding pixel unit, and the positions of the second projections are the same with each other; and
the positions of the first projections are the same with the positions of the second projections.

6. The display panel of claim 5 , wherein the sub-pixels of the pixel units disposed in the first display area comprise a plurality of first sub-pixels, a plurality of second sub-pixels and a plurality of third sub-pixels;
the first driving transistor groups comprise a plurality of first driving transistors for driving the first sub-pixels, a plurality of second driving transistors for driving the second sub-pixels and a plurality of third driving transistors for driving the third sub-pixels;
the pixel units corresponding to the first driving transistors, the second driving transistors and the third driving transistors are respectively defined as first pixel units, second pixel units and third pixel units;
in the stacking direction, the first pixel units are disposed above the first driving transistors, the second pixel units are disposed above the second driving transistors, and the third pixel units are disposed above the third driving transistors.

7. The display panel of claim 6 , wherein in the stacking direction,
the positions of the first projections of the vias of the gate electrodes of the first driving transistors on corresponding first pixel units are the same with each other,
the positions of the first projections of the vias of the gate electrodes of the second driving transistors on corresponding second pixel units are the same with each other, and
the positions of the first projections of the vias of the gate electrodes of the third driving transistors on corresponding third pixel units are the same with each other.

8. The display panel of claim 7 , wherein in the stacking direction,
the connecting lines passing through the first pixel units are overlapped with the gate electrodes of the first driving transistors, the connecting lines passing through the second pixel units are overlapped with the gate electrodes of the second driving transistors, and the connecting lines passing through the third pixel units are overlapped with the gate electrodes of the third driving transistors.

9. The display panel of claim 6 , wherein the sub-pixels of the pixel units disposed in the second display area comprise a plurality of first sub-pixels, a plurality of second sub-pixels and a plurality of third sub-pixels;
the second driving transistor groups comprise a plurality of fourth driving transistors for driving the first sub-pixels disposed in the second display area, a plurality of fifth driving transistors for driving the second sub-pixels disposed in the second display area and a plurality of sixth driving transistors for driving the third sub-pixels disposed in the second display area;
the pixel units corresponding to the fourth driving transistors, the fifth driving transistors and the sixth driving transistors are respectively defined as fourth pixel units, fifth pixel units and sixth pixel units;
in the stacking direction, the fourth pixel units are disposed above the fourth driving transistors, the fifth pixel units are disposed above the fifth driving transistors, and the sixth pixel units are disposed above the sixth driving transistors.

10. The display panel of claim 9 , wherein in the stacking direction,
the positions of the second projections of the vias of the gate electrodes of the fourth driving transistors on corresponding fourth pixel units are the same with each other,
the positions of the second projections of the vias of the gate electrodes of the fifth driving transistors on corresponding fifth pixel units are the same with each other, and
the positions of the second projections of the vias of the gate electrodes of the sixth driving transistors on corresponding sixth pixel units are the same with each other.

11. The display panel of claim 10 , wherein in the stacking direction,
the connecting lines passing through the fourth pixel units are overlapped with the gate electrodes of the fourth driving transistors, the connecting lines passing through the fifth pixel units are overlapped with the gate electrodes of the fifth driving transistors, and the connecting lines passing through the sixth pixel units are overlapped with the gate electrodes of the sixth driving transistors.

12. The display panel of claim 9 , wherein the first pixel unit, the second pixel unit and the third pixel unit are same with each other and the fourth pixel unit, the fifth pixel unit and the sixth pixel unit are same with

Assignees

• Kunshan Govisionox Optoelectronics Co Ltd

Inventors

• Chang Miao
• Zhang Lu
• Zhu Xiujian
• Hu Siming
• Han Zhenzhen

Classifications

• G09G2300/0439

  Pixel structures · CPC title

• G06F1/1686 Primary

  the I/O peripheral being an integrated camera · CPC title

• G06F1/1637

  Details related to the display arrangement, including those related to the mounting of the display in the housing · CPC title

• G09G2360/144

  the light being ambient light · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title