Array substrate, display panel and display apparatus

Patent metadata

Field	Value
Publication number	US-11668986-B2
Application number	US-202217582525-A
Country	US
Kind code	B2
Filing date	Jan 24, 2022
Priority date	Jan 27, 2021
Publication date	Jun 6, 2023
Grant date	Jun 6, 2023

Abstract

An array substrate is provided. One of a first electrode layer and a second electrode layer in the array substrate includes at least one slit electrode. The slit electrode is disposed between two adjacent data leads in the array substrate, and includes an electrode connecting portion and a plurality of first strip-shaped sub-electrodes. The electrode connecting portion includes a first connecting section parallel to and adjacent to the data lead. A width of the first strip-shaped sub-electrode gradually decreases along a direction going away from the first strip-shaped sub-electrode, and a distance between two adjacent first strip-shaped sub-electrodes in a direction parallel to an extending direction of the first connecting section gradually increases along the direction going away from the first connecting section.

First claim

What is claimed is:

1. An array substrate, comprising a base substrate, a first electrode layer, an insulating dielectric layer, and a second electrode layer; wherein the array substrate further comprises a plurality of data leads; and one of the first electrode layer and the second electrode layer comprises at least one slit electrode;
the slit electrode is disposed between two adjacent data leads, and the slit electrode comprises an electrode connecting portion and a plurality of first strip-shaped sub-electrodes arranged in sequence, one end of each of the first strip-shaped sub-electrodes being connected to the electrode connecting portion;
the electrode connecting portion comprises a first connecting section parallel to and adjacent to the data lead, wherein the plurality of first strip-shaped sub-electrodes are disposed on a same side of the first connecting section; a width of the first strip-shaped sub-electrode gradually decreases along a direction going away from the first connecting section; and a distance between two adjacent first strip-shaped sub-electrodes in a direction parallel to an extending direction of the first connecting section gradually increases along the direction going away from the first connecting section;
the first connecting section has a first edge and a second edge which are opposite to each other and are parallel to the extending direction of the first connecting section; the second edge of the first connecting section is farther from the first strip-shaped sub-electrodes than the first edge of the first connecting section is;
in the plurality of first strip-shaped sub-electrodes connected to the first connecting section, a distance between first design reference points of any two adjacent first strip-shaped sub-electrodes is equal; and
wherein in one slit electrode, the first design reference point of the first strip-shaped sub-electrode is an intersection point of a first auxiliary design line of the first strip-shaped sub-electrode and an auxiliary design line of the first connecting section, the first auxiliary design line of the first strip-shaped sub-electrode is a straight line on which an orthographic projection of the first edge of the first strip-shaped sub-electrode on the base substrate is located, and the auxiliary design line of the first connecting section is a straight line on which an orthographic projection of the first edge of the first connecting section on the base substrate is located.

2. The array substrate according to claim 1 , wherein the first connecting section comprises a first end and a second end that are opposite; the electrode connecting portion further comprises a second connecting section, a first end of the second connecting section being connected to the first end of the first connecting section;
in one slit electrode, the first strip-shaped sub-electrode extends from the first end of the first connecting section towards a side close to the second end of the first connecting section along the direction going away from the first connecting section; and
each of the first strip-shaped sub-electrodes comprises a first edge and a second edge which are opposite, and the first edge of the first strip-shaped sub-electrode is farther from a second end of the second connecting section than the second edge of the first strip-shaped sub-electrode is.

3. The array substrate according to claim 1 , wherein in one slit electrode, the distance between the first design reference points of any two adjacent first strip-shaped sub-electrodes is equal.

4. The array substrate according to claim 3 , wherein in one slit electrode, first design reference sizes of the first strip-shaped sub-electrodes are the same; and
in one slit electrode, the first design reference size of the first strip-shaped sub-electrode is a distance between the first design reference point of the first strip-shaped sub-electrode and a second design reference point of the first strip-shaped sub-electrode, the second design reference point of the first strip-shaped sub-electrode is an intersection point of a second auxiliary design line of the first strip-shaped sub-electrode and the auxiliary design line of the first connecting section, and the second auxiliary design line of the first strip-shaped sub-electrode is a straight line on which an orthographic projection of the second edge of the first strip-shaped sub-electrode on the base substrate is located.

5. The array substrate according to claim 1 , wherein in one slit electrode, part of the plurality of first strip-shaped sub-electrodes are connected to the first connecting section, and the other first strip-shaped sub-electrodes are connected to the second connecting section.

6. The array substrate according to claim 5 , wherein the second connecting section has a first edge and a second edge which are opposite, wherein the second edge of the second connecting section is farther from the first strip-shaped sub-electrodes than the first edge of the second connecting section is;
in the plurality of first strip-shaped sub-electrodes connected to the second connecting section, second design reference sizes of the first strip-shaped sub-electrodes are the same;
wherein the second design reference size of the first strip-shaped sub-electrode is a distance between a third design reference point of the first strip-shaped sub-electrode and a fourth design reference point of the first strip-shaped sub-electrode, the third design reference point of the first strip-shaped sub-electrode is an intersection point of the first auxiliary design line of the first strip-shaped sub-electrode and an auxiliary design line of the second connecting section, the fourth design reference point of the first strip-shaped sub-electrode is an intersection point of the second auxiliary design line of the first strip-shaped sub-electrode and the auxiliary design line of the second connecting section, and the auxiliary design line of the second connecting section is a straight line on which an orthographic projection of the first edge of the second connecting section on the base substrate is located.

7. The array substrate according to claim 1 , wherein in one slit electrode, for part of the first strip-shaped sub-electrodes, an end, away from the first connecting section, of the first strip-shaped sub-electrode has a third edge parallel to the extending direction of the first connecting section; a size of the third edge is 0.4 to 0.8 times a first design reference size of the first strip-shaped sub-electrode connected to the first connecting section;
wherein the first design reference size of the first strip-shaped sub-electrode is a distance between the first design reference point of the first strip-shaped sub-electrode and a second design reference point of the first strip-shaped sub-electrode, and the second design reference point of the first strip-shaped sub-electrode is an intersection point of a second auxiliary design line of the first strip-shaped sub-electrode and the auxiliary design line of the first connecting section.

8. The array substrate according to claim 5 , wherein the slit electrode further comprises a plurality of second strip-shaped sub-electrodes disposed on a same side of the first connecting section; one end of each of the second strip-shaped sub-electrodes is connected to the electrode connecting portion; the second strip-shaped sub-electrode extends from the second end of the first connecting section towards a side close to the first end of the first connecting section along the direction going away from the first connecting section, and a width of the second strip-shaped sub-electrode gradually decreases along the direction going away from the first connecting section; and
a distance between

Assignees

• Boe Technology Group Co Ltd

Inventors

• Fang Zheng
• Liang Pengxia
• Shi Ge
• Yang Song
• Liu Yujie
• Han Jiahui
• Sun Yanliu
• Choi Hyunsic
• Li Hongpeng

Classifications

• G02F1/136286 Primary

  Wiring, e.g. gate line, drain line · CPC title

• G02F1/134309 Primary

  characterised by their geometrical arrangement · CPC title

• G02F1/136277

  formed on a semiconductor substrate, e.g. of silicon · CPC title

• G02F1/1362 Primary

  Active matrix addressed cells {(G02F1/134336, G02F1/134363 take precedence)} · CPC title