Error correction code engine performing ECC decoding, operation method thereof, and storage device including ECC engine

Patent metadata

Field	Value
Publication number	US-11664826-B2
Application number	US-202117478002-A
Country	US
Kind code	B2
Filing date	Sep 17, 2021
Priority date	Dec 7, 2020
Publication date	May 30, 2023
Grant date	May 30, 2023

Abstract

A method of responding to a read request from a host includes: obtaining read data from a memory device, performing first iteration ECC decoding on the read data to generate a plurality of pieces of decoded data, selecting one of the plurality of pieces of decoded data as intermediate data as intermediate data, generating preprocessed data based on the read data and the intermediate data and performing second iteration ECC decoding on the preprocessed data when the first iteration ECC decoding fails, and outputting the intermediate data to the host when the first iteration ECC decoding succeeds.

First claim

What is claimed is:

1. A method of responding to a read request from a host, the method comprising:
obtaining read data from a memory device;
performing first iteration error correction code (ECC) decoding on the read data to generate a plurality of pieces of decoded data;
selecting one of the plurality of pieces of decoded data as intermediate data;
generating preprocessed data based on the read data and the intermediate data and performing second iteration ECC decoding on the preprocessed data when the first iteration ECC decoding fails; and
outputting the intermediate data to the host when the first iteration ECC decoding succeeds,
wherein the performing of the second iteration ECC decoding on the preprocessed data comprises:
comparing the read data to the intermediate data;
determining a reliability of the intermediate data based on a result of the comparing; and
generating the preprocessed data based on the reliability of the intermediate data.

2. The operation method of claim 1 , wherein the selecting comprises determining a piece among the plurality of pieces of decoded data having a lowest error rate as the intermediate data.

3. The operation method of claim 2 , wherein the selecting comprises:
calculating a first error rate of a first piece among the pieces of decoded data;
calculating a second error rate of a second piece among the pieces of decoded data; and
comparing the first error rate to the second error rate to determine the piece having the lowest error rate.

4. The operation method of claim 3 , wherein the first error rate is based on at least one of a checksum or a syndrome of the first piece of the decoded data.

5. The operation method of claim 1 , wherein the comparing of the read data to the intermediate data comprises comparing bits of the read data to corresponding bits of the intermediate data to determine a match therebetween.

6. The operation method of claim 5 , wherein the preprocessed data includes soft decision data, and the determining of the reliability of the intermediate data comprises, determining a reliability of a first bit value of the intermediate data as a strong level when a first bit value of the read data matches a first bit value of the intermediate data, and otherwise, determining the reliability of the first bit value of the intermediate data as a weak level.

7. The operation method of claim 5 , wherein the preprocessed data includes hard decision data, and when a first bit value of the read data does not match a first bit value of the intermediate data, a first bit value of the preprocessed data is generated by flipping the first bit value of the read data.

8. An error correction code (ECC) engine comprising:
an ECC decoder configured to perform first iteration ECC decoding on read data obtained from a memory device to generate a plurality of pieces of decoded data, and select one of the plurality of pieces as intermediate data; and
a preprocessor configured to generate preprocessed data based on the read data and the intermediate data when the first iteration ECC decoding fails,
wherein the ECC decoder performs second iteration ECC decoding by using the preprocessed data when the first iteration ECC decoding fails,
wherein the preprocessor further includes a comparator and a generator,
the comparator compares the read data to the intermediate data, determines a reliability of the intermediate data based on a result of the comparing, and
the generator generates the preprocessed data based on the reliability of the intermediate data.

9. The ECC engine of claim 8 , wherein the ECC decoder selects the one piece by determining a piece among the plurality of pieces of decoded data having a lowest error rate.

10. The ECC engine of claim 8 , wherein the preprocessor calculates a reliability of the intermediate data according to whether the read data matches the intermediate data, and generates the preprocessed data to include the intermediate data and the reliability.

11. The ECC engine of claim 8 , wherein the ECC decoder comprises a first ECC decoder and a second ECC decoder, and when decoding by the first ECC decoder fails, the preprocessor receives the intermediate data from the first ECC decoder, and provides the preprocessed data to the second ECC decoder.

12. The ECC engine of claim 11 , wherein the second ECC decoder has an error correction capability higher than that of the first ECC decoder.

13. The ECC engine of claim 8 , wherein the ECC decoder supports a plurality of decoding modes, performs a first ECC decoding according to a first decoding mode among the decoding modes, and provides the intermediate data to the preprocessor, and performs a second ECC decoding in a second decoding mode among the decoding modes on the preprocessed data received from the preprocessor, when the first ECC decoding fails.

14. The ECC engine of claim 13 , wherein the second decoding mode has an error correction capability higher than that of the first decoding mode.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Kangseok
• Yu Geunyeong
• Kwak Heeyoul
• Son Hongrak
• Shin Dongmin
• Lee Wijik
• Jun Bohwan
• Hwang Youngjun

Classifications

• H03M13/1108

  Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping · CPC title

• G06F11/1044 Primary

  with specific ECC/EDC distribution · CPC title

• H03M13/6511 Primary

  Support of multiple decoding rules, e.g. combined MAP and Viterbi decoding · CPC title

• H03M13/3707

  Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code · CPC title

• G11C29/42 Primary

  using error correcting codes [ECC] or parity check · CPC title