Always-on FinFET with camouflaged punch stop implants for protecting integrated circuits from reverse engineering

Patent metadata

Field	Value
Publication number	US-11664332-B2
Application number	US-202117157579-A
Country	US
Kind code	B2
Filing date	Jan 25, 2021
Priority date	Jan 28, 2020
Publication date	May 30, 2023
Grant date	May 30, 2023

Abstract

A camouflaged application specific integrated circuit is disclosed. The camouflaged ASIC includes at least one camouflaged FinFET, which includes a substrate of a first conductivity type, a fin, disposed on the substrate, the fin including a source region of a second conductivity type, a drain region of the second conductivity type, and a channel region of the first conductivity type. The camouflaged application specific integrated circuit also includes a gate disposed over and substantially perpendicular to the channel region, forming one or more transistor junctions with the fin. In one embodiment, the substrate includes a punch through stop (PTS) region of the second conductivity type disposed between the fin and the substrate, the PTS region electrically shorting the source region of the fin to the drain region of the fin.

First claim

What is claimed is:

1. A camouflaged application specific integrated circuit (ASIC) comprising:
at least one camouflaged FinFET, comprising:
a substrate of a first conductivity type;
a fin, disposed on the substrate, the fin including:
a source region of a second conductivity type;
a drain region of the second conductivity type;
a channel region of the first conductivity type; and

a gate disposed over and substantially perpendicular to the channel region, the gate forming one or more transistor junctions with the fin;
wherein the substrate comprises a punch through stop (PTS) region of the second conductivity type disposed between the fin and the substrate, the PTS region electrically shorting the source region of the fin to the drain region of the fin.

2. The camouflaged ASIC of claim 1 , wherein:
the first conductivity type is P-type; and
the second conductivity type is N-type.

3. The camouflaged ASIC of claim 1 , wherein:
the first conductivity type is N-type; and
the second conductivity type is P-type.

4. The camouflaged ASIC of claim 1 , wherein:
the fin further comprises:
a source side extension region disposed between the channel region and the source region; and
a drain side extension region disposed between the channel region and the drain region.

5. The camouflaged ASIC of claim 1 , wherein the fin comprises a longitudinal axis and the PTS region runs along the longitudinal axis.

6. A camouflaged FinFET, comprising:
a substrate of a first conductivity type;
a fin, disposed on the substrate, the fin including:
a source region of a second conductivity type;
a drain region of the second conductivity type;
a channel region of the first conductivity type; and

a gate disposed over and substantially perpendicular to the channel region, the gate forming one or more transistor junctions with the fin;
wherein the substrate comprises a punch through stop (PTS) region of the second conductivity type disposed between the fin and the substrate, the PTS region electrically shorting the source region of the fin to the drain region of the fin.

7. The camouflaged FinFET of claim 6 , wherein:
the first conductivity type is P-type; and
the second conductivity type is N-type.

8. The camouflaged FinFET of claim 6 , wherein:
the first conductivity type is N-type; and
the second conductivity type is P-type.

9. The camouflaged FinFET of claim 6 , wherein:
the fin further comprises:
a source side extension region disposed between the channel region and the source region; and
a drain side extension region disposed between the channel region and the drain region.

10. The camouflaged FinFET of claim 6 , wherein the fin comprises a longitudinal axis and the PTS region runs along the longitudinal axis.

11. A method of producing a camouflaged FinFET, comprising:
forming a substrate of a first conductivity type;
forming a fin on the substrate, the fin having a source region, a drain region, and a channel region;
placing punch through stop (PTS) implants of a second conductivity type between the fin and the substrate;
doping the channel region to the first conductivity type;
forming a gate dielectric over only the channel region; and
placing implants of the second conductivity type in the source region and the drain region;
wherein the PTS implants electrically short the source region of the fin to the drain region of the fin.

12. The method of claim 11 , wherein the PTS implants extend longitudinally at least from the source region to the drain region and electrically short the source region to the drain region.

13. The method of claim 12 , wherein placing punch through stop (PTS) implants of a second conductivity type between the fin and the substrate comprises:
masking the fin and substrate to expose only an area between the fin and the substrate; and
exposing the masked fin and substrate to an ion implant source.

14. The method of claim 12 , wherein:
forming the fin of the dielectric on the substrate, the fin having the source region, the drain region, and the channel region comprises:
depositing the dielectric on the substrate; and
lithographically etching the dielectric and substrate to remove the dielectric in areas other than fin;

doping the channel region to the first conductivity type comprises;
masking the fin and the substrate to expose only the channel region; and
exposing the fin and dielectric masked to expose only the channel region to an ion implant source; and

placing implants of the second conductivity type in the source region and the drain region comprises:
masking the fin and the substrate to expose only the fin; and
exposing the masked fin and substrate to a second ion implant source.

15. The method of claim 12 , further comprising:
forming gate spacers on each side of the gate dielectric; and
placing further implants of the second conductivity type in a portion of the source region and a portion of the channel region.

16. The method of claim 12 , wherein:
the first conductivity type is P-type; and
the second conductivity type is N-type.

17. The method of claim 12 , wherein:
the first conductivity type is N-type; and
the second conductivity type is P-type.

18. The method of claim 12 , wherein the fin comprises a longitudinal axis and the PTS implants run along the longitudinal axis.

19. A camouflaged FinFET, formed by performing steps comprising the steps of:
forming a substrate of a first conductivity type;
forming a fin on the substrate, the fin having a source region, a drain region, and a channel region;
placing punch through stop (PTS) implants of a second conductivity type between the fin and the substrate;
doping the channel region to the first conductivity type;
forming a gate dielectric over only the channel region; and
placing implants of the second conductivity type in the source region and the drain region;
wherein the PTS implants electrically short the source region of the fin to the drain region of the fin.

20. The camouflaged FinFET of claim 19 , wherein the PTS implants extend longitudinally at least from the source region to the drain region and electrically short the source region to the drain region.

Assignees

• Rambus Inc

Inventors

• Chow Lap Wai
• Wang Bryan J
• Baukus James P
• Cocchi Ronald P

Classifications

• H10W42/405 Primary

  using active circuits · CPC title

• H10D84/853 Primary

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D62/371

  Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current · CPC title