Metal-insulator-metal (MIM) structure supporting high voltage applications and low voltage applications

Patent metadata

Field	Value
Publication number	US-11664270-B2
Application number	US-202117222790-A
Country	US
Kind code	B2
Filing date	Apr 5, 2021
Priority date	Dec 27, 2017
Publication date	May 30, 2023
Grant date	May 30, 2023

Abstract

An apparatus is provided which includes: a first stack including a lower, a middle, and an upper layer of conductive material with insulator layers therebetween, and a second stack including the middle and upper layers with one of the insulator layers therebetween. In an example, a first of the insulator layers has a lower breakdown voltage than a second of the insulator layers. The apparatus further includes a first via over the first stack, wherein the first via is in contact with a pair of the lower, middle and upper layers that have the first of the insulator layers therebetween. The apparatus further includes a second via over the second stack, wherein the second via extends through the upper layer and is in contact with the middle layer. In an example, the second via is isolated from a sidewall of the upper layer by a spacer.

First claim

I claim:

1. An integrated circuit (IC) structure, comprising:
a first stack comprising a first layer, a second layer, and a third layer each comprising a first conductive material, a first insulator layer comprising a first thickness between the first layer and the second layer and a second insulator layer comprising a second thickness between the second layer and the third layer, wherein the third layer is above the first layer;
a second stack laterally adjacent to the first stack, wherein the second stack comprises all but the first layer of the first stack;
a first via comprising a second conductive material, the first via partially through the first stack and wherein the first via comprises a first lateral thickness; and
a second via comprising the second conductive material extending through the second stack, the second via comprising a variable second lateral thickness in contact with the second layer and the first insulator layer.

2. The IC structure of claim 1 , wherein the first thickness is greater than or less than the second thickness.

3. The IC structure of claim 1 , wherein the first insulator layer is continuous between the first and the second stack.

4. The IC structure of claim 1 , wherein the first via and the second via each have a plan view profile that is substantially circular and wherein the first and the variable second lateral thicknesses are each a respective diameter of the first via and the second via.

5. The IC structure of claim 4 , wherein the IC structure further comprises a first spacer laterally adjacent to and between the second via and each of the third layer and at least a portion of the second insulator layer, wherein the first spacer comprises a first dielectric material.

6. The IC structure of claim 5 , wherein the second via has a first diameter adjacent to the third layer and the second insulator and a second diameter adjacent to the second layer and adjacent to the first insulator layer, wherein the second diameter is greater than the first diameter.

7. The IC structure of claim 5 , the spacer is laterally adjacent to and between the second via and an entire sidewall of the second insulator layer.

8. The IC structure of claim 1 , wherein the first insulator layer is discontinuous between the first via and the second via.

9. The IC structure of claim 1 , wherein the first layer, the second layer and the third layer of the first stack are each respectively separated from the first layer, the second layer and the third layer of the second stack.

10. The IC structure of claim 1 , wherein the second via extends to a level below the first insulator layer.

11. The IC structure of claim 1 , further comprising:
a third stack comprising a fourth layer comprising the conductive material;
the first insulator layer on the fourth layer;
a plurality of vias comprising the second conductive material through the first insulator layer, wherein individual ones of the plurality of vias are in contact with the fourth layer; and wherein the individual ones of the plurality of vias have a plan view profile that is substantially circular and a diameter that varies with height of individual ones of the plurality of vias.

12. The IC structure of claim 11 further comprises a second spacer comprising a second dielectric material laterally adjacent to a portion of each of the individual ones of the plurality of vias, wherein the diameter is greatest adjacent to the first insulator layer.

13. The IC structure of claim 12 further comprises a third spacer laterally adjacent to and between the second via and both the third layer and at least a portion of the second insulator layer, wherein the second spacer and the third spacer are on a same plane, and wherein the second spacer and the third spacer each comprise a same dielectric.

14. A system comprising:
a memory to store instructions; and
a processor circuitry coupled to the memory, the processor circuitry to execute the instructions, wherein one of the memory, the processor circuitry, or another component of the system comprises:
a first stack comprising a first, a second, and a third layer of a first conductive material and an insulator layer between each conductive material, wherein a first insulator layer comprising a first thickness is between the first layer and the second layer and a second insulator layer comprising a second thickness is between the second and the third layer;
a second stack laterally adjacent to the first stack, wherein the second stack comprises all but the first layer of the first stack;
a first via comprising a second conductive material, the first via partially through the first stack and wherein the first via comprises a first lateral thickness; and
a second via comprising the second conductive material extending through the second stack, the second via comprising a variable lateral thickness in contact with the second layer and the first insulator layer.

15. The system of claim 14 , further comprising a third via on at least a portion of the second stack, wherein the third via is in contact with the third layer.

16. The system of claim 14 , further comprising a display subsystem coupled with the processor circuitry.

17. A method of fabricating an integrated circuit structure, the method comprising:
forming a material layer stack comprising a first insulator layer between a pair of conductive layers above a second insulator layer;
patterning a portion of the material layer stack into a plurality of stacks and exposing at least a portion of the second insulator layer;
forming a dielectric on the plurality of stacks and on the exposed portion of the second insulator layer;
patterning a portion of a first of the plurality of stacks to form an opening and forming a first via in the first opening;
patterning a second of the plurality of stacks and the second insulator to form a second opening and forming a second via in the second opening;
patterning the dielectric and the second insulator to form a third opening and forming a third via in the third opening; and
forming a spacer adjacent to each of the second via and the third via.

18. The method of claim 17 , wherein the pair of conductive layers comprises a first conductive layer and a second conductive layer above the first conductive layer, and wherein forming the first via further comprises:
patterning an opening in the second conductive layer and in the first insulator layer and exposing the first conductive layer; and
depositing a conductive material in the first via on a portion of the first conductive layer.

19. The method of claim 18 , wherein forming the spacer adjacent to the second via further comprises forming a first spacer adjacent to a sidewall of the second conductive layer and a sidewall of the first insulator layer in the second of the plurality of stacks prior to forming the second via.

20. The method of claim 19 , wherein forming the spacer adjacent to the third via further comprises forming a second spacer adjacent to a portion of a sidewall of the dielectric in the third opening, prior to forming the third via.

Assignees

• Intel Corp

Inventors

• Lin Kevin

Classifications

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/083 Primary

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title