Contactless wafer separator

Patent metadata

Field	Value
Publication number	US-11664257-B2
Application number	US-202117480161-A
Country	US
Kind code	B2
Filing date	Sep 21, 2021
Priority date	Sep 21, 2021
Publication date	May 30, 2023
Grant date	May 30, 2023

Abstract

The present disclosure is directed to a wafer container including: a housing configured for transporting a plurality of wafers, wherein the plurality of wafers are stacked on a base of the housing in a first direction; a plurality of wafer separator rings; each of the wafer separator rings configured to encircle a wafer of the plurality of wafers in a second direction that is substantially perpendicular to the first direction, each of the wafer separator rings including a top surface and a bottom surface, defining a thickness there between extending in the first direction, which is about 0.3 mm-1.4 mm; and each of the wafer separator rings including an inner side wall and an outer side wall defined by an inner diameter and an outer diameter, respectively, in the second direction, wherein the inner diameter of the wafer separator ring is greater than 300 mm and configured to be spaced apart from the wafer it is encircling.

First claim

The invention claimed is:

1. A wafer container comprising:
a housing configured for transporting a plurality of wafers, wherein the plurality of wafers are stacked on a base of the housing in a first direction;
a plurality of wafer separator rings;
wherein each of the plurality of wafer separator rings is configured to encircle a wafer of the plurality of wafers in a second direction that is substantially perpendicular to the first direction;
wherein each of the plurality of wafer separator rings comprises a top surface and a bottom surface, defining a thickness there between extending in the first direction, which is about 0.3 mm-1.4 mm; and
each of the plurality of wafer separator rings comprises an inner side wall and an outer side wall defined by an inner diameter and an outer diameter, respectively, in the second direction;
wherein the inner diameter of each of the wafer separator rings is greater than 300 mm and configured to be spaced apart from the wafer it is encircling; and
wherein at least one ridge is positioned on the inner side wall of each of the plurality of wafer separator rings.

2. The wafer container of claim 1 , wherein the plurality of wafer separator rings comprise a rigid polymer material.

3. The wafer container of claim 2 , wherein the rigid polymer material comprises polycarbonate.

4. The wafer container of claim 1 , wherein each of the plurality of wafer separator rings further comprises at least one ridge positioned along the top surface of the wafer separator ring.

5. The wafer container of claim 1 , wherein a first ridge is positioned along the inner side wall of each of the plurality of wafer separator rings and a second ridge is positioned along the top surface of each of the plurality of wafer separator rings.

6. The wafer container of claim 1 , wherein the inner diameter of each of the plurality of wafer separator rings is at least 0.01 mm greater than an outer diameter of the wafer it is encircling.

7. The wafer container of claim 1 , further comprising the plurality of wafers.

8. The wafer container of claim 7 , wherein each wafer of the plurality of wafers comprises a plurality of dies with solder bumps disposed on the plurality of dies.

9. The wafer container of claim 1 , further comprising a carrier layer and at least one support ring supporting the carrier layer, the support ring comprising an inner diameter that is greater than the inner diameter of the plurality of wafer separator rings and an outer diameter that is at least as great as, or greater than, the outer diameter of the plurality of wafer separator rings.

10. The wafer container of claim 9 , wherein the support ring comprises a metal material.

11. The wafer container of claim 1 , further comprising a plurality of carrier layers, wherein each wafer of the plurality of wafers is configured to be disposed on each of the plurality of carrier layers.

12. The wafer container of claim 11 , wherein the carrier layer comprises an adhesive material.

13. The wafer container of claim 12 , wherein the adhesive material comprises polyethylene terephthalate material.

14. The wafer container of claim 1 , wherein the top surface or the bottom surface comprises one or more ridges.

15. A wafer separator ring comprising:
a top surface and a bottom surface defining a thickness there between extending in a first direction;
at least one ridge positioned thereon;
wherein the wafer separator ring is configured to encircle a wafer in a second direction that is substantially perpendicular to the first direction;
wherein the thickness of the wafer separator ring is about 0.3 mm-1.4 mm; and
the wafer separator ring comprises an inner side wall and an outer side wall defined by an inner diameter and an outer diameter in the second direction, respectively;
wherein at least one ridge is positioned on the inner side wall; and
wherein the inner diameter of the wafer separator ring is greater than 300 mm.

16. The wafer separator ring of claim 15 , wherein the wafer separator ring comprises a rigid polymer material.

17. The wafer container of claim 16 , wherein the rigid polymer material comprises polycarbonate.

18. A method for stacking wafers comprising:
providing a wafer container for housing a plurality of wafers, wherein the plurality of wafers are stacked in a first direction;
disposing each of the plurality of wafers on a carrier layer;
providing a wafer separator ring encircling each wafer of the plurality of wafers,
wherein the wafer separator ring comprises:
a top surface and a bottom surface defining a thickness there between extending in the first direction, which is greater than a thickness of the wafer it is encircling;
an inner side wall and an outer side wall defined by an inner diameter and an outer diameter in the second direction, respectively; and
at least one ridge positioned on the inner side wall;
wherein the inner diameter of the wafer separator ring is greater than an outer diameter of the wafer such that the wafer separator ring is spaced apart from the wafer it is encircling.

19. The method claim 18 , the stacking of the plurality of wafers further comprising positioning a top wafer on a second ridge of a bottom wafer separator ring.

Assignees

• Intel Corp

Inventors

• Dhruvkumar Varshalaxmi Bhatt
• Biggs John
• Wong Shaw Fong

Classifications

• H10P72/3402

  Mechanical parts of transfer devices · CPC title

• H10P72/3412 Primary

  Batch transfer of wafers · CPC title

• H10P72/1912 Primary

  characterised by shock absorbing elements, e.g. retainers or cushions · CPC title

• B65G57/005

  by using insertions or spacers between the stacked layers · CPC title

• Y02P80/30

  Reducing waste in manufacturing processes; Calculations of released waste quantities · CPC title