Security of embedded devices through a device lifecycle with a device identifier

Patent metadata

Field	Value
Publication number	US-11663146-B2
Application number	US-202016806227-A
Country	US
Kind code	B2
Filing date	Mar 2, 2020
Priority date	Jun 27, 2019
Publication date	May 30, 2023
Grant date	May 30, 2023

Abstract

An apparatus includes a database with device profiles, and a device programmer. The device programmer includes instructions. The instructions, when read and executed by a processor, cause the device programmer to identify a device identifier of an electronic device. The device programmer is further caused to, based upon the device identifier, access device data from the database. The device programmer is further caused to, based upon the device data, determine an area of memory of the electronic device that can be written. The device programmer is further caused to, based on the determination of the area of memory of the electronic device that can be written, write data to the area of memory.

First claim

What is claimed is:

1. An apparatus, comprising:
a database including a plurality of device profiles; and,
a device programmer including instructions, the instructions, when read and executed by a processor, cause the device programmer to:
identify a first device identifier of a first electronic device;
based upon the first device identifier, access first device data from the database;
based upon the first device data, determine a first area of memory of the first electronic device that can be written; and
based on the determination of the first area of memory of the first electronic device that can be written, write data to the first area of memory of the first electronic device.

2. The apparatus of claim 1 , wherein the first device data includes a first memory map of the first device, the first memory map configured to define the first area of memory of the first electronic device as programmable.

3. The apparatus of claim 2 , wherein the first memory map is further configured to define a second area of memory of the first electronic device that is not programmable.

4. The apparatus of claim 3 , wherein the first memory map is further configured to define the second area of memory of the first electronic device as unseen from usage of the first electronic device.

5. The apparatus of claim 1 , wherein the device programmer is further configured to, upon writing data to the first area of memory of the first electronic device, replace the first device identifier with a second device identifier on the first electronic device.

6. The apparatus of claim 5 , wherein the second device identifier is configured to define a third area of memory that can be written.

7. The apparatus of claim 6 , wherein the second device identifier is configured to prevent one or more other apparatuses from writing data to the first area of memory of the first electronic device.

8. The apparatus of claim 5 , wherein the second device identifier is associated with a second memory map of the first electronic device, the second memory map configured to define the third area of memory of the first electronic device as programmable.

9. The apparatus of claim 5 , wherein the second device identifier is configured to define that the first area of memory is unprogrammable.

10. The apparatus of claim 5 , wherein the device programmer is further configured to:
identify a third device identifier of a second electronic device; and
based upon the third device identifier, determine that a different device programmer is configured to write data to the second electronic device instead of the device programmer.

11. The apparatus of claim 5 , wherein:
the first device identifier is configured to allow access through a first memory map to debug features of the first electronic device; and
the second device identifier is configured to deny access through a second memory map to debug features of the first electronic device.

12. The apparatus of claim 1 , wherein the first device identifier is configured to be replaced by a second device identifier.

13. The apparatus of claim 12 , wherein the second device identifier is configured to define a third area of memory that can be written.

14. The apparatus of claim 12 , wherein the second device identifier is further configured to prevent writes of data to the first area of the memory.

15. The apparatus of claim 12 , wherein the second device identifier is further configured to define that the first area of memory is unprogrammable.

16. The apparatus of claim 12 , wherein:
the first device identifier is configured to allow access through a first memory map to debug features of the apparatus; and
the second device identifier is configured to deny access through a second memory map to debug features of the apparatus.

17. An apparatus, comprising:
a memory; and
a first device identifier configured to:
denote a phase of production for the apparatus; and
allow access to a first area of the memory that can be written.

18. The apparatus of claim 17 , wherein the first device identifier is configured to prevent programming of a second area of the memory.

19. The apparatus of claim 18 , wherein the second area of the memory is not mapped for use of the apparatus.

20. A method, comprising:
accessing a first electronic device;
identifying a first device identifier of the first electronic device;
based upon the first device identifier, accessing first device data from a database including a plurality of device profiles;
based upon the first device data, determining a first area of memory of the first electronic device that can be written; and
based on the determination of the first area of memory of the first electronic device that can be written, writing data to the first area of memory of the first electronic device.

21. A method, comprising:
providing access to a first electronic device for a device programmer;
providing a first device identifier to the device programmer from a memory; and
based on the first device identifier:
denoting a phase of production for the first electronic device; and
allowing access to a first area of the memory that can be written.

Assignees

• Microchip Tech Inc

Inventors

• Simmons Michael

Classifications

• G06F3/0653

  Monitoring storage devices or systems · CPC title

• G06F21/72 Primary

  in cryptographic circuits · CPC title

• G06F3/0616

  in relation to life time, e.g. increasing Mean Time Between Failures [MTBF] · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0637

  Permissions · CPC title