Information processing apparatus, communication system, information processing method, and program

Patent metadata

Field	Value
Publication number	US-11659439-B2
Application number	US-201615777425-A
Country	US
Kind code	B2
Filing date	Sep 21, 2016
Priority date	Nov 30, 2015
Publication date	May 23, 2023
Grant date	May 23, 2023

Abstract

A communication system includes a first information processing apparatus and a second information processing apparatus. The first information processing apparatus controls to determine an information amount to be used for a receipt acknowledgment response to packets to be transmitted to a second information processing apparatus on the basis of information relating to the packets and notifies the second information processing apparatus of that determined information amount. The second information processing apparatus controls to return the receipt acknowledgment response to the packets transmitted from the first information processing apparatus to the first information processing apparatus on the basis of the information amount notified from the first information processing apparatus.

First claim

The invention claimed is:

1. An information processing apparatus comprising:
transmitting circuitry configured to transmit an ADDBA Request including first Block Ack size information indicating a first size to another information processing apparatus; and
receiving circuitry configured to receive an ADDBA Response including second Block Ack size information indicating a second size from the another information processing apparatus, the second size of the second Block Ack size information being equal to or less than the first size of the first Block Ack size information requested by the information processing apparatus,
wherein the transmitting circuitry is configured to transmit, after exchanging the ADDBA Request and the ADDBA Response, a data frame to the another information processing apparatus, and
wherein the receiving circuitry is configured to receive a Block Ack frame in response to the data frame, the Block Ack frame including third Block Ack size information indicating a third size and a Block Ack Bitmap of the third size; and
control circuitry configured to determine the first size each time data related to the ADDBA Request is transmitted to the another information processing apparatus to notify the another information processing apparatus of the first size,
wherein the first size is determined from 16, 32, 64, 128, 256, 512, 1024 or 2048 bits.

2. The information processing apparatus according to claim 1 , wherein the first Block Ack size information is based on a total number of the packets included in the data frame to be transmitted or a length from a start sequence numeral to an end sequence numeral among sequence numerals corresponding to the packets.

3. The information processing apparatus according to claim 1 , wherein the packets included in the data frame to be transmitted are packets that have not been successfully transmitted to the another information processing apparatus.

4. The information processing apparatus according to claim 1 , further comprising control circuitry configured to concatenate packets in agreement with the first size among packets to be transmitted and transmit the concatenated packets in the data frame to the another information processing apparatus.

5. The information processing apparatus according to claim 1 , further comprising control circuitry configured to concatenate packets to be transmitted and transmit the concatenated packets in the data frame to the another information processing apparatus, while determining a size of the Block Ack Bitmap as the first size.

6. The information processing apparatus according to claim 1 , further comprising control circuitry configured to, in a case where the second size different from the first size is notified from another information processing apparatus after notifying the first size, the control circuitry newly determines the second size as the first size to be used for the Block Ack frame.

7. The information processing apparatus according to claim 1 , further comprising control circuitry configured to determine the first size when the another information processing apparatus returns the Block Ack frame.

8. The information processing apparatus according to claim 7 , wherein, in a case where the Block Ack frame that is compressed is received from the another information processing apparatus, the control circuitry is further configured to acquire contents of the compressed Block Ack frame that has been received on the basis of the third Block Ack size information.

9. An information processing apparatus comprising:
receiving circuitry configured to receive an ADDBA Request including first Block Ack size information indicating a first size from another information processing apparatus; and
transmitting circuitry configured to transmit an ADDBA Response including second Block Ack size information indicating a second size to the another information processing apparatus, the second size of the second Block Ack size information being the same as or smaller than the first size of the first Block Ack size information requested by the information processing apparatus,
wherein the receiving circuitry is configured to receive after exchanging the ADDBA Request and the ADDBA Response, a data frame from the another information processing apparatus, and
wherein the transmitting circuitry is configured to transmit a Block Ack frame in response to the data frame, the Block Ack frame including third Block Ack size information indicating a third size and a Block Ack Bitmap of the third size; and
the first size being determined by the another information processing apparatus each time data related to the ADDBA Request is transmitted from the another information processing apparatus to notify the information processing apparatus of the first size,
wherein the first size is determined from 16, 32, 64, 128, 256, 512, 1024 or 2048 bits.

10. The information processing apparatus according to claim 9 , further comprising control circuitry configured to, in a case where the first size notified from the another information processing apparatus exceeds performance of the information processing apparatus related to wireless communication, determine the second size different from the first size within a range of the performance and notify the another information processing apparatus of the second size.

11. The information processing apparatus according to claim 9 , further comprising control circuitry configured to compress the Block Ack frame on the basis of the third size.

12. The information processing apparatus according to claim 9 , wherein the first size is greater than 64 bits.

13. The information processing apparatus according to claim 1 , wherein the first size is greater than 64 bits.

14. The information processing apparatus according to claim 9 , wherein the first size is 16 bits.

15. The information processing apparatus according to claim 9 , wherein the first size is 32 bits.

16. The information processing apparatus according to claim 1 , wherein the first size is 16 bits.

17. The information processing apparatus according to claim 1 , wherein the first size is 32 bits.

Assignees

• Sony Corp

Inventors

• Sakai Eisuke
• Tanaka Yusuke

Classifications

• H04W28/04

  Error control · CPC title

• H04W28/06 Primary

  Optimizing {the usage of the radio link}, e.g. header compression, information sizing {, discarding information (system modifying transmission characteristic according to link quality by modifying frame length H04L1/0007; dynamic adaptation of the packet size for flow control or congestion control H04L47/365)} · CPC title

• H04W84/12

  WLAN [Wireless Local Area Networks] · CPC title

• H04L1/1896

  ARQ related signaling · CPC title

• H04W28/065 Primary

  using assembly or disassembly of packets · CPC title