Low power clock gating cell and an integrated circuit including the same

Patent metadata

Field	Value
Publication number	US-11658656-B2
Application number	US-202117515607-A
Country	US
Kind code	B2
Filing date	Nov 1, 2021
Priority date	Nov 26, 2020
Publication date	May 23, 2023
Grant date	May 23, 2023

Abstract

A clock gating cell including: a first circuit configured to receive an enable signal and an inverted output clock signal and generate a first signal through a first node; a second circuit configured to receive the first signal and generate an inverted first signal; a third circuit configured to receive the first signal, the inverted first signal, and an input clock signal, generate the first signal by being connected to the first circuit through the first node, and generate the inverted output clock signal through a second node; and a fourth circuit configured to receive the first signal, generate the inverted output clock signal by being connected to the third circuit through the second node, and generate the output clock signal, wherein the third circuit includes a pair of transistors receiving the input clock signal.

First claim

What is claimed is:

1. A clock gating cell, comprising:
a first circuit configured to receive an enable signal and an inverted output clock signal and generate a first signal through a first node;
a second circuit configured to receive the first signal and generate an inverted first signal;
a third circuit configured to receive the first signal, the inverted first signal, and an input clock signal, generate the first signal by being connected to the first circuit through the first node, and generate the inverted output clock signal through a second node; and
a fourth circuit configured to directly receive the first signal, generate the inverted output clock signal by being connected to the third circuit through the second node, and generate an output clock signal,
wherein the third circuit comprises a pair of transistors receiving the input clock signal.

2. The clock gating cell of claim 1 , wherein the third circuit comprises a first transistor and a second transistor each receiving the input clock signal,
the first transistor is configured to control a charging path of the first node and the second node based on the input clock signal, and
the second transistor is configured to control a discharging path of the first node and the second node based on the input clock signal.

3. The clock gating cell of claim 1 , wherein the first circuit comprises:
a first inverter configured to generate an inverted enable signal by inverting the enable signal;
a first transistor connected between a power voltage node and the first node and receiving the inverted output clock signal; and
a second transistor and a third transistor connected in series between the first node and a ground node,
wherein the second transistor receives the inverted enable signal, and
the third transistor receives the inverted output clock signal.

4. The clock gating cell of claim 1 , wherein the clock gating cell is configured to further receive a scan enable signal,
the first circuit comprises a NOR gate configured to receive the enable signal and the scan enable signal and generate a second signal.

5. The clock gating cell of claim 1 , wherein the third circuit comprises:
a first transistor connected between a power voltage node and a third node and controlled by the inverted first signal;
a second transistor connected between the third node and the first node and controlled by the inverted enable signal;
a third transistor connected between the second node and the first node and controlled by the input clock signal;
a fourth transistor connected between the first node and a fourth node and controlled by the inverted first signal;
a fifth transistor connected between the second node and the fourth node and controlled by the first signal; and
a sixth transistor connected between a ground node and the fourth node and controlled by the input clock signal.

6. The clock gating cell of claim 5 , wherein a polarity of the third transistor and a polarity of the sixth transistor are opposite to each other.

7. The clock gating cell of claim 5 , the third transistor is configured to control a charging path of the first node and the second node based on the input clock signal, and
the sixth transistor is configured to control a discharging path of the first node and the second node based on the input clock signal.

8. The clock gating cell of claim 5 , wherein the second circuit generates a delayed first signal by inverting the inverted first signal, and
the fifth transistor is applied with the delayed first signal.

9. The clock gating cell of claim 1 , wherein the fourth circuit comprises:
a first transistor connected between a power voltage and the second node and controlled by the first signal; and
a first inverter configured to generate the output clock signal by inverting the inverted output clock signal.

10. The clock gating cell of claim 9 , wherein the second circuit is configured to generate a delayed first signal by inverting the inverted first signal, and
the first transistor is applied with the delayed first signal.

11. The clock gating cell of claim 10 , wherein the fourth circuit further comprises at least one second transistor connected between the power voltage node and the second node and controlled by the input clock signal.

12. The clock gating cell of claim 11 , wherein a number of the at least one second transistor corresponds to a number of a plurality of transistors, which are included in the third circuit and are connected between the second node and a ground node.

13. An integrated circuit comprising a clock gating cell that receives at least one control signal and an input clock signal and generates an output clock signal,
wherein the clock gating cell comprises:
a first circuit comprising a first function circuit configured to generate a first signal through a first node based on the at least one control signal and a first keeper circuit configured to maintain a voltage level of the first signal;
a second circuit configured to receive the first signal and generate an inverted first signal;
a third circuit comprising a second function circuit configured to generate the first signal through the first node based on the at least one control signal, a second keeper circuit configured to maintain a voltage level of the first signal, a first charge circuit configured to generate an inverted output clock signal by charging a second node based on the first signal, and a discharge circuit configured to discharge the second node; and
a fourth circuit comprising a second charge circuit configured to generate the inverted output clock signal by charging the second node based on the first signal, and
the third circuit comprises a pair of transistors receiving the input clock signal,
wherein a polarity of the control signal applied to the first charge circuit and a polarity of the control signal applied to the second charge circuit are opposite to each other.

14. The integrated circuit of claim 13 , wherein the first keeper circuit is input with the inverted output clock signal,
the second keeper circuit is input with the inverted first signal, and
the discharge circuit is input with the first signal.

15. The integrated circuit of claim 13 , wherein the first charge circuit includes a p-type field effect transistor (PFET) transistor applied with the inverted first signal, and
the second charge circuit includes a PFET transistor applied with the first signal.

16. The integrated circuit of claim 14 , wherein the third circuit further comprises a first transistor that is input with the input clock signal and is connected to the first charge circuit and the second charge circuit,
the second node is charged by the first charge circuit when the first transistor is turned on, and
the second node is charged by the second charge circuit when the first transistor is turned off.

17. The integrated circuit of claim 16 , wherein the third circuit further comprises a second transistor configured to control a discharging path of the first node and the second node.

18. A latch circuit, comprising:
a first circuit configured to receive an inverted output clock signal and a data signal and generate a first signal through a first node;
a second circuit configured to receive the data signal, an input clock signal, and an output signal, generate the first signal by being connected to the first circuit through the first node, and generate the inverted output clock signal through a second node;
a third circuit configured to generate the inverted output clock

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hwang Hyunchul
• Lee Youngo

Classifications

• H03K19/0016 Primary

  by using a control or a clock signal, e.g. in order to apply power supply · CPC title

• H03K19/094

  using field-effect transistors · CPC title

• G06F1/3237 Primary

  by disabling clock generation or distribution · CPC title

• H03K17/6871 Primary

  the output circuit comprising more than one controlled field-effect transistor · CPC title

• H03K3/356

  Bistable circuits · CPC title