Amplifier circuit, corresponding comparator device and method

Patent metadata

Field	Value
Publication number	US-11658625-B2
Application number	US-202117141812-A
Country	US
Kind code	B2
Filing date	Jan 5, 2021
Priority date	Jan 31, 2020
Publication date	May 23, 2023
Grant date	May 23, 2023

Abstract

A preamplifier circuit comprises a first pair of transistors and a second pair of transistors having current flow paths therethrough coupled at first and second output nodes and providing first and second current flow lines intermediate a supply node and ground. The two pairs of transistors comprise: first and second input transistors located intermediate the outputs nodes and one of the supply node and ground providing respective input nodes, first and second load transistors intermediate the output nodes and the other of the supply node and ground. The load transistors have control terminals capacitively coupled to the other of the supply node and ground and a reset switch arrangement is provided periodically activatable to short the first output node, the second output node as well as the control terminals of the first load transistor and the second load transistor.

First claim

The invention claimed is:

1. A circuit, comprising:
a first input transistor having conductive terminals respectively coupled to a first output node and one of a supply node and ground, the first input transistor having a control terminal coupled to a first input node;
a second input transistor having conductive terminals respectively coupled to a second output node and the one of the supply node and ground, the second input transistor having a control terminal coupled to a second input node;
a capacitance having a first side coupled to the other of the supply node and ground and having a second side;
a first load transistor having conductive terminals respectively coupled to the first output node and the other of the supply node and ground, the first load transistor having a control terminal coupled to the second side of the capacitance;
a second load transistor having conductive terminals respectively coupled to the second output node and the other of the supply node and ground, the second load transistor having a control terminal coupled to the second side of the capacitance; and
a reset switch circuit configured to, in response to being activated, short together all of the first output node, the second output node, the control terminal of the first load transistor and the control terminal of the second load transistor.

2. The circuit of claim 1 , comprising:
a current supply source having an anode and a cathode, wherein one of the anode and the cathode is coupled to one of the supply node and ground, and wherein the other of the anode and the cathode is configured to sink or source both a first current flowing through the first input transistor and the first load transistor and a second current flowing through the second input transistor and the second load transistor.

3. The circuit of claim 1 , wherein the first input transistor and the second input transistor have a first polarity in common and the first load transistor and the second load transistor have a second polarity, opposite the first polarity, in common.

4. The circuit of claim 1 , wherein the first input transistor, the second input transistor, the first load transistor and the second load transistor are field-effect transistors (FETs).

5. The circuit of claim 4 , wherein the first input transistor, the second input transistor, the first load transistor and the second load transistor are metal-oxide-semiconductor FETs (MOSFETs).

6. The circuit of claim 1 , wherein the reset switch circuit is configured to, in response to being activated, set the first output node to zero voltage.

7. A comparator, comprising:
a first input transistor having conductive terminals respectively coupled to a first output node and one of a supply node and ground, the first input transistor having a control terminal coupled to a first input node;
a second input transistor having conductive terminals respectively coupled to a second output node and the one of the supply node and ground, the second input transistor having a control terminal coupled to a second input node;
a capacitance having a first side coupled to the other of the supply node and ground and having a second side;
a first load transistor having conductive terminals respectively coupled to the first output node and the other of the supply node and ground, the first load transistor having a control terminal coupled to the second side of the capacitance;
a second load transistor having conductive terminals respectively coupled to the second output node and the other of the supply node and ground, the second load transistor having a control terminal coupled to the second side of the capacitance;
a reset switch circuit configured to, in response to being activated, short together all of the first output node, the second output node, the control terminal of the first load transistor and the control terminal of the second load transistor; and
a latch circuit having input nodes coupled to the first output node and the second output node, respectively, and output nodes, wherein in response to receiving a first input signal at the first input node and a second input signal at the second input node, the latch circuit is configured to provide between the respective output nodes a differential latched signal that based on an outcome of a comparison between the first input signal and the second input signal.

8. The comparator of claim 7 , comprising:
a current supply source having an anode and a cathode, wherein one of the anode and the cathode is coupled to one of the supply node and ground, and wherein the other of the anode and the cathode is configured to sink or source both a first current flowing through the first input transistor and the first load transistor and a second current flowing through the second input transistor and the second load transistor.

9. The comparator of claim 7 , wherein the first input transistor and the second input transistor have a first polarity in common and the first load transistor and the second load transistor have a second polarity, opposite the first polarity, in common.

10. The comparator of claim 7 , wherein the first input transistor, the second input transistor, the first load transistor and the second load transistor are field-effect transistors (FETs).

11. The comparator of claim 10 , wherein the first input transistor, the second input transistor, the first load transistor and the second load transistor are metal-oxide-semiconductor FETs (MOSFETs).

12. The comparator of claim 7 , wherein the reset switch circuit is configured to, in response to being activated, set the first output node to zero voltage.

13. A method, comprising:
supplying a first input signal to a first input node and a second input signal to a second input node, wherein:
the first input node is coupled to a control terminal of a first input transistor, and the first input transistor has conductive terminals respectively coupled to a first output node and one of a supply node and ground, and
the second input node is coupled to a control terminal of a second input transistor, and the second input transistor has conductive terminals respectively coupled to a second output node and the one of the supply node and ground,

outputting an output signal over a first output node and a second output node, wherein:
the first output node is coupled to a first conductive terminal of a first load transistor, the first load transistor having a second conductive terminal coupled to the other of the supply node and ground and a control terminal coupled to a first side of a capacitance, and the capacitance having a second side coupled to the other of the supply node and ground, and
the second output node is coupled to a first conductive terminal of a second load transistor, the second load transistor having a second conductive terminal coupled to the other of the supply node and ground and a control terminal coupled to the first side of the capacitance, and

activating a reset switch circuit to short together all of the first output node, the second output node, the control terminal of the first load transistor and the control terminal of the second load transistor.

14. The method of claim 13 , comprising:
setting the output signal to zero voltage in response to activating, at a subsequent activation event, the reset switch circuit.

15. The method of claim 14 , comprising:
separating subsequent activation events of the reset switch circuit by respective output signal integration intervals; and
collecting output signals over the first and second output nodes at respective ends of the output signal integrat

Assignees

• St Microelectronics Srl

Inventors

• Modaffari Roberto

Classifications

• H03K5/2481

  with at least one differential stage · CPC title

• G01R19/0038 Primary

  Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller (comparing pulses or pulse trains according to amplitude) · CPC title

• H03F3/45479 Primary

  characterised by the way of common mode signal rejection · CPC title

• H03F2200/375

  Circuitry to compensate the offset being present in an amplifier · CPC title

• H03K5/24

  the characteristic being amplitude · CPC title