Display apparatus comprising different types of thin film transistors and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-11658189-B2
Application number	US-202117196805-A
Country	US
Kind code	B2
Filing date	Mar 9, 2021
Priority date	Dec 26, 2018
Publication date	May 23, 2023
Grant date	May 23, 2023

Abstract

A display apparatus includes a substrate; a pixel driving circuit on the substrate; and a display unit connected with the pixel driving circuit, wherein the pixel driving circuit includes a first thin film transistor and a second thin film transistor, wherein the first thin film transistor includes, a first gate electrode on the substrate, a first active layer spaced apart from the first gate electrode and overlapping at least a part of the first gate electrode, a first source electrode connected with the first active layer; and a first drain electrode spaced apart from the first source electrode and connected with the first active layer, and wherein the second thin film transistor includes, a second active layer on the substrate, and a second gate electrode spaced apart from the second active layer and partially overlapping at least a part of the second active layer, wherein the first gate electrode is disposed between the substrate and the first active layer, the second active layer is disposed between the substrate and the second gate electrode, and the first gate electrode and the second gate electrode are disposed at an opposite side with respect to the second active layer.

First claim

What is claimed is:

1. A method for manufacturing a display apparatus comprising:
sequentially depositing a first conductive material layer, a first insulating material layer and a first active material layer on a substrate;
forming a first source electrode and a first drain electrode that are spaced apart from each other and connected with the first active material layer;
forming a first gate electrode from the first conductive material layer, a first gate insulating film from the first insulating material, and a first active layer from the first active material by a selective etching process;
forming a first insulating interlayer on the first active layer;
forming a second active material layer including a plurality of patterns on the first insulating interlayer;
forming a second gate insulating film and a second gate electrode on at least a part of the second active material layer; and
conductivizing the second active material layer in the area that does not overlap the second gate electrode to form a conducting portion in the second active material layer.

2. The method according to claim 1 , further comprising forming an etch stopper between the first source electrode and the first drain electrode.

3. The method according to claim 2 , wherein the etch stopper is formed of a same material as that of the first insulating interlayer.

4. The method according to claim 1 , wherein a part of the first source electrode and a part of the first gate electrode vertically overlap each other and form a storage capacitor.

5. The method according to claim 4 , further comprising:
forming a second insulating interlayer on the first source electrode; and
forming a third capacitor electrode overlapping at least a part of the first source electrode on the second insulating interlayer.

6. The method according to claim 1 , wherein a plasma treatment or a hydrogen treatment is carried out in the conductivizing the second active material layer.

7. The method according to claim 1 , wherein the first source electrode and the first drain electrode are formed in the conductivizing the second active material layer in the area that does not overlap the second gate electrode.

8. A display apparatus comprising:
a substrate;
a pixel driving circuit on the substrate; and
a display unit connected with the pixel driving circuit,
wherein the pixel driving circuit includes a first thin film transistor and a second thin film transistor,
wherein the first thin film transistor includes,
a first gate electrode on the substrate,
a first active layer spaced apart from the first gate electrode and overlapping at least a part of the first gate electrode,
a first source electrode connected with the first active layer; and
a first drain electrode spaced apart from the first source electrode and connected with the first active layer, and
wherein the second thin film transistor includes,
a second active layer on the substrate, and
a second gate electrode spaced apart from the second active layer and partially overlapping at least a part of the second active layer,
wherein the first gate electrode is disposed between the substrate and the first active layer,
the second active layer is disposed between the substrate and the second gate electrode, and
the first gate electrode and the second gate electrode are disposed at an opposite side with respect to the second active layer, and
wherein the display apparatus further comprises a first insulating interlayer on the first active layer, and the second active layer is disposed on the first insulating interlayer,
wherein the first active layer and the second active layer are disposed at opposite sides with respect to the first insulating interlayer.

9. The display apparatus according to claim 8 , wherein the second active layer is disposed at a same layer as the first source electrode and the first drain electrode.

10. The display apparatus according to claim 8 , wherein the first source electrode and the first drain electrode are disposed on the first insulating interlayer and are connected with the first active layer through contact holes.

11. The display apparatus according to claim 10 , each of the first source electrode and the first drain electrode has a recess in the contact holes.

12. The display apparatus according to claim 10 , each of the first source electrode and the first drain electrode directly contacts the first active layer through the contact holes.

13. The display apparatus according to claim 8 , further comprising an etch stopper on the first active layer, wherein the etch stopper is disposed at a same layer as the first insulating interlayer and is formed of a same material as the first insulating interlayer.

14. The display apparatus according to claim 8 , wherein the second active layer, the first source electrode and the first drain electrode are formed of an oxide semiconductor material.

15. The display apparatus according to claim 8 , wherein at least one of the first active layer and the second active layer includes:
a first oxide semiconductor layer; and
a second oxide semiconductor layer disposed on the first oxide semiconductor layer.

16. The display apparatus according to claim 8 , further comprising a data line and a driving voltage line,
wherein the data line and the driving voltage line are disposed at a same layer as the first gate electrode.

17. The display apparatus according to claim 8 , further comprising:
a second insulating interlayer on the first source electrode and the first drain electrode; and
a planarization layer on the second insulating interlayer,
wherein the display unit is disposed on the planarization layer.

18. The display apparatus according to claim 17 , further comprising a storage capacitor connected with the first thin film transistor,
wherein the storage capacitor includes:
a first capacitor electrode formed as one body with the first source electrode; and
a second capacitor electrode formed as one body with the first gate electrode.

19. The display apparatus according to claim 18 , wherein the storage capacitor further includes a third capacitor electrode spaced from the first capacitor electrode and disposed on the second insulating interlayer.

20. The display apparatus according to claim 8 , wherein the first thin film transistor functions as a driving transistor that drives the display unit.

21. The display apparatus according to claim 8 , wherein the second thin film transistor functions as a switching transistor.

Assignees

• Lg Display Co Ltd

Inventors

• Jang Jaeman
• Park Sehee
• Kim Daehwan
• Yun Pilsang

Classifications

• H10D86/471

  having different architectures, e.g. having both top-gate and bottom-gate TFTs · CPC title

• H10D86/423 Primary

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• H10D86/021

  of multiple TFTs · CPC title