Multilayer electronic component

Patent metadata

Field	Value
Publication number	US-11657966-B2
Application number	US-202117338124-A
Country	US
Kind code	B2
Filing date	Jun 3, 2021
Priority date	Sep 18, 2020
Publication date	May 23, 2023
Grant date	May 23, 2023

Abstract

A multilayer electronic component includes: a body including first and second dielectric layers alternately disposed in a first direction; and external electrodes disposed on opposing end surfaces, respectively. A first internal electrode exposed to a first end surface and a first dummy pattern spaced apart from the first internal electrode and exposed to a second end surface are disposed on the first dielectric layer. A second internal electrode exposed to the second end surface and a second dummy pattern spaced apart from the second internal electrode and exposed to the first end surface are disposed on the second dielectric layer. The first and second internal electrodes include first and second main portions, respectively, and the first main portion and the second main portion are arranged in a staggered manner in a width direction.

First claim

What is claimed is:

1. A multilayer electronic component comprising:
a body having first and second surfaces opposing each other in a first direction, third and fourth surfaces connected to the first and second surfaces and opposing each other in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other in a third direction, the body including first and second dielectric layers alternately disposed in the first direction; and
external electrodes disposed on the third and fourth surfaces, respectively,
wherein a first internal electrode exposed to the third surface and a first dummy pattern spaced apart from the first internal electrode and exposed to the fourth surface are disposed on the first dielectric layer,
a second internal electrode exposed to the fourth surface and a second dummy pattern spaced apart from the second internal electrode and exposed to the third surface are disposed on the second dielectric layer,
the first internal electrode includes a first main portion disposed to be spaced apart from the fifth and sixth surfaces and first and second side portions disposed on opposite side surfaces of the first main portion, respectively, and exposed to the third surface, the first and second side portions being different in size and disposed asymmetrically relative to a central axis of the first dielectric layer in the second direction,
the second internal electrode includes a second main portion disposed to be spaced apart from the fifth and sixth surfaces and third and fourth side portions disposed on opposite side surfaces of the second main portion, respectively, and exposed to the fourth surface, the third and fourth side portions being different in size and disposed asymmetrically relative to a central axis of the second dielectric layer in the second direction, and
the first main portion and the second main portion are arranged in a staggered manner in the third direction.

2. The multilayer electronic component of claim 1 , wherein a difference between a distance from the first main portion to the fifth surface and a distance from the second main portion to the fifth surface is 0.05 times or more and 0.2 times or less a width of the first main portion.

3. The multilayer electronic component of claim 2 , wherein the first and second main portions have substantially the same width as each other.

4. The multilayer electronic component of claim 1 , wherein widths of the first and second side portions decrease in a direction away from the third surface, and widths of the third and fourth side portions decrease in a direction away from the fourth surface.

5. The multilayer electronic component of claim 4 , wherein the first side portion is disposed on a first side surface, close to the sixth surface, among the opposite side surfaces of the first main portion, and the second side portion is disposed on a second side surface among the opposite side surfaces of the first main portion, and
the third side portion is disposed on a first side surface, close to the sixth surface, among the opposite side surfaces of the second main portion and the fourth side portion is disposed on a second side surface among the opposite side surfaces of the second main portion.

6. The multilayer electronic component of claim 5 , wherein a width of the first side portion exposed to the third surface is smaller than a width of the second side portion exposed to the third surface, and
a width of the third side portion exposed to the fourth surface is greater than a width of the fourth side portion exposed to the fourth surface.

7. The multilayer electronic component of claim 5 , wherein a width of the first side portion exposed to the third surface and a width of the fourth side portion exposed to the fourth surface is 0.2 times or more and 1.0 times or less a distance from the second main portion to the fifth surface, and
a width of the second side portion exposed to the third surface and a width of the third side portion exposed to the fourth surface is 0.2 times or more and 1.0 times or less a distance from the first main portion to from the fifth surface.

8. The multilayer electronic component of claim 5 , wherein a length of an interface at which the first side portion and the first main portion are in contact with each other is smaller than a length of an interface at which the second side portion and the first main portion are in contact with each other, and
a length of an interface at which the third side portion and the second main portion are in contact with each other is greater than a length of an interface at which the fourth side portion and the second main portion are in contact with each other.

9. The multilayer electronic component of claim 5 , wherein a length at which the first side portion and the first main portion are in contact with each other and a length at which the fourth side portion and the second main portion are in contact with each other is 0.4 times or more and 3.0 times or less a distance from the second main portion to the fifth surface, and
a length of an interface at which the second side portion and the first main portion are in contact with each other and a length of an interface at which the third side portion and the second main portion are in contact with each other is 0.4 times or more and 3.0 times or less a distance from the first main portion to the fifth surface.

10. The multilayer electronic component of claim 5 , wherein the second side portion is disposed to partially overlap the second main portion, and
the third side portion is disposed to partially overlap the first main portion.

11. The multilayer electronic component of claim 4 , wherein a width of the first dummy pattern decreases in a direction away from the fourth surface, and
a width of the second dummy pattern decreases in a direction away from the third surface.

12. The multilayer electronic component of claim 4 , wherein a width of the first dummy pattern exposed to the fourth surface is 0.95 times to 1.05 times a width of the second internal electrode exposed to the fourth surface, and
a width of the second dummy pattern exposed to the third surface is 0.95 times to 1.05 times a width of the first internal electrode exposed to the third surface.

13. The multilayer electronic component of claim 4 , wherein a width of the first dummy pattern exposed to the fourth surface is substantially the same as a width of the second internal electrode exposed to the fourth surface, and
a width of the second dummy pattern exposed to the third surface is substantially the same as a width of the first internal electrode exposed to the third surface.

14. A multilayer electronic component comprising:
a body including first and second dielectric layers alternately disposed in a stacked direction, first and second internal electrodes disposed on the first and second dielectric layers, respectively, and first and second dummy patterns disposed on the first and second dielectric layers and spaced apart from the first and second internal electrodes, respectively; and
external electrodes disposed on first and second end surfaces of the body, respectively, opposing each other in a length direction,
wherein the first internal electrode and the first dummy pattern are exposed to the first and second end surfaces, respectively, and the second internal electrode and the second dummy pattern are exposed to the second and first end surfaces, respectively, and
outer edges of the first and second internal electrodes deviate asymmetrically relative to a length-wise central axis of the first and second d

Assignees

• Samsung Electro Mech

Inventors

• Kim Kyeong Jun
• Jun Ho In
• Kim Seul Gi
• Chun Jin Sung
• Yun Jun Ho

Classifications

• H01G4/012

  Form of non-self-supporting electrodes · CPC title

• H01G4/30 Primary

  Stacked capacitors (H01G4/33 takes precedence) · CPC title

• H01G4/232 Primary

  electrically connecting two or more layers of a stacked or rolled capacitor · CPC title

• H01G4/224

  Housing; Encapsulation · CPC title

• H01G4/018

  Dielectrics · CPC title