Drive circuit and drive method, shift register and display device

Patent metadata

Field	Value
Publication number	US-11657752-B2
Application number	US-202117559253-A
Country	US
Kind code	B2
Filing date	Dec 22, 2021
Priority date	Jun 30, 2021
Publication date	May 23, 2023
Grant date	May 23, 2023

Abstract

A drive circuit, a drive method, a shift register, and a display device are provided. The drive circuit includes a control module, an output module, and a protect module. The control module is electrically connected to a start signal line, first and second clock signal lines, first and second potential signal lines, and first and second nodes, and is configured to transmit a voltage signal to the first and the second nodes in response to first and second clock signals. The output module is electrically connected to the first and second potential signal lines, an output wire, and the first and second nodes. The protect module is configured to transmit an effective voltage signal to the first node in response to a control signal in a first state of the drive circuit such that the output module transmits an ineffective voltage signal to the output wire.

First claim

What is claimed is:

1. A drive circuit, comprising:
a control module electrically connected to a start signal line, a first clock signal line, a second clock signal line, a first potential signal line, a second potential signal line, a first node, and a second node, wherein the drive circuit has a first state and a display state, wherein the first state is prior to the display state, and the control module is configured to transmit a voltage signal to the first node and the second node in response to a first clock signal and a second clock signal;
an output module electrically connected to the first potential signal line, the second potential signal line, an output wire, the first node, and the second node, wherein the output module is configured to transmit a voltage signal to the output wire in response to a control signal of the first node and a control signal of the second node; and
a protect module, wherein in the first state, the protect module is configured to transmit an effective voltage signal to the first node in response to a control signal in such a manner that the output module transmits an ineffective voltage signal to the output wire,
wherein the control module comprises:
a third control unit electrically connected to the second clock signal line, the first node, the second node, and a third node, and configured to transmit a voltage signal to the first node in response to a voltage signal of the third node, the second clock signal, and the voltage signal of the second node; and
wherein the third control unit comprises:
a ninth transistor comprising a control electrode electrically connected to the third node, a first electrode electrically connected to the second clock signal line, and a second electrode;
a tenth transistor comprising a control electrode electrically connected to the second clock signal line, a first electrode electrically connected to the second electrode of the ninth transistor, and a second electrode electrically connected to the first node;
an eleventh transistor comprising a control electrode electrically connected to the second node, a first electrode electrically connected to the second potential signal line, and a second electrode electrically connected to the first node; and
a first capacitor comprising a first plate electrically connected to the third node, and a second plate electrically connected to the second electrode of the ninth transistor.

2. The drive circuit according to claim 1 , wherein the protect module comprises a first transistor, wherein the first transistor comprises a control electrode electrically connected to a first control signal line, a first electrode electrically connected to a first signal line, and a second electrode electrically connected to the first node.

3. The drive circuit according to claim 1 , wherein in the first state, the protect module is further configured to transmit an ineffective voltage signal to the second node in response to a control signal in such a manner that the output module does not transmit an effective voltage signal to the output wire.

4. The drive circuit according to claim 3 , wherein the protect module further comprises a second transistor, wherein the second transistor comprises a control electrode electrically connected to a second control signal line, a first electrode electrically connected to a second signal line, and a second electrode electrically connected to the second node.

5. The drive circuit according to claim 4 , wherein the protect module comprises a first transistor, wherein the first transistor comprises a control electrode electrically connected to a first control signal line, a first electrode electrically connected to a first signal line, and a second electrode electrically connected to the first node; and
wherein the control electrode of the first transistor is electrically connected to the control electrode of the second transistor, the first signal line is the first potential signal line, and the second signal line is the second potential signal line; or
the first transistor and the second transistor are both P type transistors, the first electrode of the first transistor is electrically connected to the control electrode of the first transistor, and the second signal line is the second potential signal line; or
the first transistor and the second transistor are both N type transistors, the first electrode of the second transistor is electrically connected to the control electrode of the second transistor, and the first signal line is the first potential signal line.

6. The drive circuit according to claim 1 , wherein the control module comprises:
a first control unit electrically connected to the first clock signal line, the first potential signal line, the second node, and the third node, and configured to transmit a voltage signal to the third node in response to a first clock signal and the voltage signal of the second node; and
a second control unit electrically connected to the start signal line, the first clock signal line, the second clock signal line, the second potential signal line, the third node, and the second node, and configured to transmit a voltage signal to the second node in response to the first clock signal, the second clock signal, and the voltage signal of the third node.

7. The drive circuit according to claim 6 , wherein the second control unit comprises:
a third transistor comprising a control electrode electrically connected to the first clock signal line, a first electrode electrically connected to the start signal line, and a second electrode electrically connected to the second node;
a fourth transistor comprising a control electrode electrically connected to the third node, a first electrode electrically connected to the second potential signal line, and a second electrode electrically connected to a fourth node; and
a fifth transistor comprising a control electrode electrically connected to the second clock signal line, a first electrode electrically connected to the fourth node, and a second electrode electrically connected to the second node.

8. The drive circuit according to claim 7 , wherein in the first state, the protect module is further configured to transmit an ineffective voltage signal to the fourth node in response to a control signal, and
in the first state, the fifth transistor transmits the ineffective voltage signal of the fourth node to the second node in response to the second clock signal in such a manner that the output module does not transmit an effective voltage signal to the output wire.

9. The drive circuit according to claim 8 , wherein the protect module further comprises a sixth transistor, wherein the sixth transistor comprises a control electrode electrically connected to a third control signal line, a first electrode electrically connected to the second potential signal line, and a second electrode electrically connected to the fourth node.

10. The drive circuit according to claim 6 , wherein the first control unit comprises:
a seventh transistor comprising a control electrode electrically connected to the first clock signal line, a first electrode electrically connected to the first potential signal line, and a second electrode electrically connected to the third node; and
an eighth transistor comprising a control electrode electrically connected to the second node, a first electrode electrically connected to the first clock signal line, and a second electrode electrically connected to the third node.

11. The drive circuit according to claim 1 , further comprising:
a second capacitor comprising a first plate electrically connected to the second potential signal line, and a second plate electri

Assignees

• Wuhan Tianma Micro Electronics Co Ltd

Inventors

• Wang Yajun
• Sun Jianming

Classifications

• G09G2330/04

  Display protection · CPC title

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2330/026

  Arrangements or methods related to booting a display · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title