Information processing apparatus and reset control method

Patent metadata

Field	Value
Publication number	US-11657125-B2
Application number	US-202017021451-A
Country	US
Kind code	B2
Filing date	Sep 15, 2020
Priority date	Sep 20, 2019
Publication date	May 23, 2023
Grant date	May 23, 2023

Abstract

There is provided an information processing apparatus that includes a first processor configured to verify a validity of a program, a control circuit configured to issue a system reset signal in a case where there is no access from outside for a predetermined period, and a second processor configured to execute the program that has been determined as valid by the first processor, and to become accessible to the control circuit after the program is initiated. The first processor is configured to access the control circuit before the second processor becomes accessible to the control circuit.

First claim

What is claimed is:

1. An information processing apparatus comprising:
a first processor configured to verify a validity of a program;
a control circuit configured to issue a system reset signal in a case where there is no access from outside for a predetermined period; and
a second processor configured to execute the program that has been determined as valid by the first processor, and to become accessible to the control circuit after the program is initiated, wherein
the first processor is configured to access the control circuit before the second processor becomes accessible to the control circuit, and

the first processor is configured to periodically output a first clear signal to the control circuit at an output cycle that is shorter than the predetermined period and thereby cause the control circuit to clear a timer value.

2. The information processing apparatus according to claim 1 , wherein
the first processor is configured to stop periodic output of the first clear signal in a case where it is determined that the program is valid.

3. The information processing apparatus according to claim 1 , wherein
the first processor is configured to notify the control circuit that a verification of the program is complete in a case where it is determined that the program is valid; and
the control circuit is configured to start monitoring a second clear signal from the second processor in response to the notification from the first processor that the verification is complete.

4. The information processing apparatus according to claim 3 , wherein
the second processor is configured to, while operating, output the second clear signal to the control circuit at an output cycle that is shorter than the predetermined period and thereby cause the control circuit to clear the timer value.

5. The information processing apparatus according to claim 1 , wherein
the control circuit is configured to count a number of times the first clear signal has been inputted from the first processor and, in a case where the number of inputs exceeds a threshold, not to clear the timer value in response to the first clear signal being inputted.

6. The information processing apparatus according to claim 1 , wherein
the control circuit is configured to request the first processor to output the first clear signal and, in a case where the first clear signal is not inputted from the first processor in response to the request, issue the system reset signal.

7. The information processing apparatus according to claim 1 , wherein
the first processor is configured to restore the program using a restoration version of the program in a case where it is determined that the program is invalid; and
the first processor is configured to access the control circuit while restoring the program.

8. The information processing apparatus according to claim 1 , wherein
the first processor is configured to output the first clear signal to the control circuit before the second processor becomes accessible to the control circuit; and
the control circuit is configured to clear the timer value and stop timekeeping in response to the first clear signal being inputted.

9. The information processing apparatus according to claim 8 , wherein
the first processor is configured to notify the control circuit that a verification of the program is complete in a case where it is determined that the program is valid; and
the control circuit is configured to restart the timekeeping in response to the notification from the first processor that the verification is complete.

10. The information processing apparatus according to claim 1 , wherein
the program comprises a basic input/output system, BIOS, program of the information processing apparatus.

11. The information processing apparatus according to claim 1 , wherein the first processor is configured to access the control circuit by outputting the first clear signal to cause the control circuit to clear the timer value so that a timeout of a timer for triggering issuance of the system reset signal is delayed.

12. A reset control method performed in an information processing apparatus that includes:
a first processor configured to verify a validity of a program;
a control circuit configured to issue a system reset signal in a case where there is no access from outside for a predetermined period; and
a second processor configured to execute the program that has been determined as valid by the first processor, and to become accessible to the control circuit after the program is initiated, the method comprising:
accessing, by the first processor, the control circuit before the second processor becomes accessible to the control circuit; and
periodically outputting, by the first processor, a first clear signal to the control circuit at a shorter output cycle than the predetermined period to cause the control circuit to clear a timer value.

13. The reset control method according to claim 12 , further comprising:
stopping, by the first processor, periodic output of the first clear signal in a case where it is determined that the program is valid.

14. The reset control method according to claim 12 , further comprising:
notifying, by the first processor, the control circuit that a verification of the program is complete in a case where it is determined that the program is valid; and
starting, by the control circuit, to monitor a second clear signal from the second processor in response to the notification from the first processor that the verification is complete.

15. The reset control method according to claim 14 , further comprising:
while the second processor is operating, outputting, by the second processor, the second clear signal to the control circuit at an output cycle that is shorter than the predetermined period and thereby causing the control circuit to clear the timer value.

16. The reset control method according to claim 12 , further comprising:
counting, by the control circuit, a number of times the first clear signal has been inputted from the first processor, wherein
the control circuit does not clear the timer value in response to the first clear signal being inputted in a case where the number of inputs exceeds a threshold.

17. The reset control method according to claim 12 , further comprising:
requesting, by the control circuit, the first processor to output the first clear signal, wherein
in a case where the first clear signal is not inputted from the first processor in response to the request, the control circuit issues the system reset signal.

18. The reset control method according to claim 12 , further comprising:
restoring, by the first processor, the program using a restoration version of the program in a case where it is determined that the program is invalid, wherein
the first processor accesses the control circuit while restoring the program.

19. The reset control method according to claim 12 , wherein
the first processor outputs the first clear signal to the control circuit before the second processor becomes accessible to the control circuit, and
the method further comprises the control circuit clearing the timer value and stopping timekeeping in response to the clear signal being inputted.

Assignees

• Canon Kk

Inventors

• Ozawa Manabu
• Yamashita Takahiro

Classifications

• G06F9/44589

  Program code verification, e.g. Java bytecode verification, proof-carrying code (high-level semantic checks G06F8/43; prevention of errors by analysis, debugging or testing of software G06F11/36) · CPC title

• G06F9/445

  Program loading or initiating (bootstrapping G06F9/4401; security arrangements for program loading or initiating G06F21/57) · CPC title

• G06F21/575 Primary

  Secure boot · CPC title

• G06F21/52

  during program execution, e.g. stack integrity {; Preventing unwanted data erasure; Buffer overflow} · CPC title

• G06F9/542

  Event management; Broadcasting; Multicasting; Notifications · CPC title