Storage device and method for operating storage device

Patent metadata

Field	Value
Publication number	US-11656963-B2
Application number	US-202217679451-A
Country	US
Kind code	B2
Filing date	Feb 24, 2022
Priority date	Oct 4, 2018
Publication date	May 23, 2023
Grant date	May 23, 2023

Abstract

A storage device includes an integrity checking module checking integrity of data stored in a first host memory buffer (HMB) address of an HMB in a host coupled to the storage device, and an HMB mapping module mapping, if the integrity checking module determines the data as corrupted, the first HMB address to a second address.

First claim

What is claimed is:

1. A method of operating a storage device, the method comprising:
checking integrity of data stored at a first host memory buffer (HMB) address of an HMB in a host coupled to the storage device; and
mapping the first HMB address to a second address when the data is determined as corrupted as a result of the checking of the integrity of the data.

2. The method for operating the storage device of claim 1 , further comprising:
writing data to the HMB;
writing checking data for checking integrity of the data to the HMB or the storage device;
reading the data from the HMB; and
reading the checking data from the HMB or the storage device,
wherein the checking of the integrity of the data comprises checking integrity of the data, using the checking data.

3. The method for operating the storage device of claim 1 ,
wherein the second address corresponds to a second HMB address in the HMB different from the first HMB address.

4. The method for operating the storage device of claim 1 ,
wherein the second address corresponds to an internal memory address of an internal memory located inside the storage device.

5. The method for operating the storage device of claim 1 , further comprising:
managing a mapping table storing information on address mapping from the first HMB address to the second address.

6. The method for operating the storage device of claim 5 , further comprising:
storing the mapping table in a non-volatile memory disposed inside the storage device; and
acquiring information on the address mapping from the mapping table stored in the non-volatile memory, when the storage device is rebooted.

7. The method for operating the storage device of claim 5 , further comprising:
initializing the mapping table storing information on the address mapping.

8. The method for operating the storage device of claim 1 , further comprising:
comparing a number of times that the data accessed using the first HMB address is determined as corrupted, to a predetermined threshold,
wherein the mapping of the first HMB address to the second address is performed in accordance with a result of the comparing.

9. The method for operating the storage device of claim 8 , further comprising:
managing a count table storing information on the number of times that the data accessed using the first HMB address is determined as corrupted.

10. The method for operating the storage device of claim 1 , further comprising:
providing information on the mapping of the first HMB address to the second address to the host,
wherein the information on the mapping includes at least one of information on the first HMB address indicating a location determined as having a defect in the HMB, information on the second address, and information on a number of times that the data accessed using the first HMB address is determined as corrupted.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Yeon Woo
• Kwon Jea Young
• Jun Walter

Classifications

• G06F12/0868 Primary

  Data transfer between cache memory and other subsystems, e.g. storage devices or host systems · CPC title

• G06F11/073 Primary

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

• G06F11/0796

  Safety measures, i.e. ensuring safe condition in the event of error, e.g. for controlling element · CPC title

• G06F12/0873 Primary

  Mapping of cache memory to specific storage devices or parts thereof · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title