Adaptive memory consistency in disaggregated datacenters

US11656796B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11656796-B2
Application numberUS-202117219505-A
CountryUS
Kind codeB2
Filing dateMar 31, 2021
Priority dateMar 31, 2021
Publication dateMay 23, 2023
Grant dateMay 23, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A data processor includes a fabric-attached memory (FAM) interface for coupling to a data fabric and fulfilling memory access instructions. A requestor-side adaptive consistency controller coupled to the FAM interface requests notifications from a fabric manager for the fabric-attached memory regarding changes in requestors authorized to access a FAM region which the data processor is authorized to access. If a notification indicates that more than one requestor is authorized to access the FAM region, fences are activated for selected memory access instructions in a local application.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for use with a fabric-attached memory system including a fabric-attached memory and a plurality of requestors coupled to the fabric-attached memory through a fabric, comprising: requesting notifications from a fabric manager regarding changes in requestors authorized to access a fabric-attached memory region; and in response to a notification from the fabric manager indicating that more than one requestor is authorized to access the fabric-attached memory region, causing fences to be activated for selected memory access instructions. 2. The method of claim 1 , further comprising, in response to a notification from the fabric manager indicating that a single requestor is authorized to access the fabric-attached memory region, mapping the fabric-attached memory region as a write-back memory region for the single requestor. 3. The method of claim 2 , further comprising, in response to the notification from the fabric manager indicating that more than one requestor is authorized to access the fabric-attached memory region, for each requestor so authorized: if the requestor is configured to issue local fence commands, causing local fence commands to be issued for the selected memory access instructions and mapping the fabric-attached memory region as write-through memory for the requestor; and if the requestor is not configured to issue local fence commands, mapping the fabric-attached memory region as uncacheable. 4. The method of claim 1 , wherein causing fences to be activated includes, in response to recognizing the selected memory access instructions as indicating dependencies between requestors, causing a requestor-side adaptive consistency controller to add fence commands for the selected memory access instructions. 5. The method of claim 4 , wherein recognizing the selected memory access instructions is performed by processor instruction microcode running at each respective requestor authorized to access the fabric-attached memory region. 6. The method of claim 4 , further comprising inserting requestor fabric interface markers into an application during compilation in response to recognizing consistency primitives and consistency constructs. 7. The method of claim 4 , wherein recognizing the selected memory access instructions is based on recognizing instructions in a predetermined list of instruction types and instruction prefixes associated with synchronization of data between threads. 8. The method of claim 1 , further comprising, at each requestor authorized to access the fabric-attached memory region, maintaining a table of the requestors authorized to access the fabric-attached memory region and updating the table responsive to each of the notifications. 9. The method of claim 8 , wherein the table comprises at least a fabric-attached memory region identifier and a number of compute requestors authorized to access the fabric-attached memory region. 10. A data processor comprising: a processing core executing an application; a fabric-attached memory interface coupled to the processing core and adapted to couple to a data fabric and fulfill memory access instructions from the processing core to a fabric-attached memory; a requestor-side adaptive consistency controller coupled to the processing core and the fabric-attached memory interface and operable to: request notifications from a fabric manager for the fabric-attached memory regarding changes in requestors authorized to access a fabric-attached memory region which the data processor is authorized to access; and responsive to a notification from the fabric manager indicating that more than one requestor is authorized to access the fabric-attached memory region, cause fences to be activated for selected memory access instructions in a local application. 11. The data processor of claim 10 , wherein the requestor-side adaptive consistency controller further operates to, in response responsive to a notification from the fabric manager indicating that a single requestor is authorized to access the fabric-attached memory region, cause the fabric-attached memory region to be mapped as a write-back memory region. 12. The data processor of claim 11 , wherein the requestor-side adaptive consistency controller further operates to, in response to the notification from the fabric manager indicating that more than one requestor is authorized to access the fabric-attached memory region: if the data processor is configured to issue local fence commands, cause local fence commands to be issued for the selected memory access instructions and mapping the fabric-attached memory region as write-through memory; and if the data processor is not configured to issue local fence commands, cause the fabric-attached memory region to be mapped as uncacheable. 13. The data processor of claim 10 , further comprising processor instruction microcode stored in tangible non-transitory memory accessible by the processor core and executable by the processing core for recognizing the selected memory access instructions. 14. The data processor of claim 13 , wherein the processor instruction microcode executes, responsive to recognizing the selected memory access instructions as indicating dependencies between requestors, to notify the requestor-side adaptive consistency controller of the recognized selected memory access instructions causing it to insert requestor-side fence commands into memory commands to the fabric-attached memory interface. 15. The data processor of claim 13 , wherein recognizing the selected memory access instructions includes response to recognizing indicators in the local application comprising one of consistency primitives and consistency constructs. 16. The data processor of claim 13 , wherein recognizing the selected memory access instructions includes recognizing fabric interface markers inserted into the application during compilation. 17. The data processor of claim 10 , wherein the requestor-side adaptive consistency controller maintains a table of the requestors authorized to access the fabric-attached memory region and updates the table responsive to the notification. 18. The data processor of claim 17 , wherein the table comprises at least a fabric-attached memory region identifier and a number of compute requestors authorized to access the fabric-attached memory region. 19. A fabric-attached memory system, comprising: a fabric-attached memory; a data fabric coupled to the fabric-attached memory; a fabric manager coupled to the data fabric and operable to authorize and deauthorize requestors to access memory regions of the fabric-attached memory; a plurality of data processors coupled to the data fabric, each including a processing core executing an application, a fabric-attached memory interface, and a requestor-side adaptive consistency controller coupled to the processing core and the fabric-attached memory interface and operable to: request notifications from the fabric manager regarding changes in requestors authorized to access a fabric-attached memory region which the data processor is authorized to access; and responsive to a notification from the fabric manager indicating that more than one requestor is authorized to access the fabric-attached memory region, cause fences to be activated for selected memory access instructions in a local application. 20. The fabric-attached memory system of claim 19 , wherein the requestor-side adaptive consistency controller further operates to, in response responsive to a no

Assignees

Inventors

Classifications

  • G06F3/0659Primary

    Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

  • Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS] · CPC title

  • by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights (G06F12/1458 takes precedence) · CPC title

  • Dependency mechanisms, e.g. register scoreboarding · CPC title

  • Controller construction arrangements · CPC title

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Frequently asked questions

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What does patent US11656796B2 cover?
A data processor includes a fabric-attached memory (FAM) interface for coupling to a data fabric and fulfilling memory access instructions. A requestor-side adaptive consistency controller coupled to the FAM interface requests notifications from a fabric manager for the fabric-attached memory regarding changes in requestors authorized to access a FAM region which the data processor is authorize…
Who is the assignee on this patent?
Advanced Micro Devices Inc
What technology area does this patent fall under?
Primary CPC classification G06F3/0659. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue May 23 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).