Computing system and method for sharing device memories of different computing devices

US11656779B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11656779-B2
Application numberUS-202117412273-A
CountryUS
Kind codeB2
Filing dateAug 26, 2021
Priority dateOct 21, 2020
Publication dateMay 23, 2023
Grant dateMay 23, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A computing system includes a host computing device and a slave computing device. The host computing device comprises a host processor, a host device memory and a host address mapping management. The host address mapping management manages a system memory page table, and converts, in response to a data access request from a processing process run on the host processor, requested virtual addresses into host device physical addresses based on the system memory page table to allow the processing process to access corresponding host storage units. The slave computing device includes a slave processor callable by the host processor to assist the host processor in running the processing processes, a slave device memory and a slave address mapping management unit. The slave address mapping unit converts, in response to a data access request of the processing process, requested virtual addresses into slave device physical addresses based on the slave device memory page table, to allow the slave processor to access corresponding slave storage units to assist the host processor in running the processing process.

First claim

Opening claim text (preview).

What is claimed is: 1. A computing system, comprising: a host computing device, the host computing device comprising: a host processor for running one or more processing processes; a host device memory having a plurality of host storage units addressable and accessible through respective host device physical addresses, and the host device memory storing, for each of the processing processes, a system memory page table indicating mapping relationships between virtual addresses of each of the processing processes and system physical addresses, wherein the host device physical addresses are a part of the system physical addresses; and a host address mapping management unit for managing the system memory page table, and for converting, in response to a data access request from a processing process of the processing processes running on the host processor, requested virtual addresses into host device physical addresses based on the system memory page table to allow the processing process running on the host processor to access corresponding host storage units; a slave computing device coupled to the host computing device through a data bus to exchange data therewith, wherein the slave computing device comprises: a slave processor callable by the host processor to assist the host processor in running the processing processes; a slave device memory having a plurality of slave storage units that can be addressable and accessible through respective slave device physical addresses, wherein the slave device physical addresses are a part of the system physical addresses; wherein the slave device memory stores a slave device memory page table including at least a part of the system memory page table, and the part of the system memory page table comprises mapping relationships between virtual addresses and system physical addresses which is requested and received by the slave computing device from the host computing device according to a data access request of a processing process of the processing processes running on the slave computing device processor, wherein the mapping relationships are used for the processing process running on the slave processor, and the slave device memory page table comprises mapping relationships between virtual addresses of data requested to be accessed and slave device physical addresses; and a slave address mapping management unit for converting, in response to the data access request of the processing process running on the slave processor, requested virtual addresses into slave device physical addresses based on the slave device memory page table, to allow the slave processor to access corresponding slave storage units to assist the host processor in running the processing processes; wherein the host address mapping management unit is also for managing the system memory page table, and for converting, in response to the data access request of the processing process running on the host processor, requested virtual addresses into slave device physical addresses based on the system memory page table to allow the processing processes running on the host processor to access corresponding slave storage units; and the slave address mapping management unit is also for converting, in response to a data access request of the processing process running on the slave processor, requested virtual addresses into host device physical addresses based on the slave device memory page table, to allow the slave processor to access corresponding host storage units to assist the host processor in running the processing processes. 2. The computing system of claim 1 , wherein the slave device memory page table is updated when the system memory page table is updated. 3. The computing system of claim 1 , wherein the processing process running on the host processor is a virtual machine process, and the virtual addresses are virtual machine physical addresses provided by the virtual machine process; wherein the host device memory is configured to further store a virtual machine memory page table that represents mapping relationships between virtual machine virtual addresses and virtual machine physical addresses, and wherein the slave device memory page table comprises mapping relationships between virtual machine virtual addresses and slave device physical addresses. 4. The computing system of claim 1 , wherein each mapping relationship between a virtual address and a system physical address in the slave device memory page table is associated with a corresponding processing process, and the slave address mapping management unit is configured to only allow each processing process to access system physical addresses based on the mapping relationships between virtual addresses and system physical addresses which are associated with the processing process. 5. The computing system of claim 4 , wherein each mapping relationship between a virtual address and a system physical address in the slave device memory page table is associated with a corresponding processing process and a corresponding access authority, and the slave address mapping management unit is configured to only allow each processing process to access system physical addresses based on the mapping relationships between virtual addresses and system physical addresses and access authorities which are associated with the processing process. 6. The computing system of claim 5 , wherein the data access request comprises a process identifier to indicate a processing process requesting access and a virtual address requested to be accessed. 7. The computing system of claim 4 , wherein the data access request comprises a process identifier to indicate a processing process requesting access and a virtual address requested to be accessed. 8. A method for sharing device memories of different computing devices in a computing system, wherein the computing system comprises a host computing device having a host device memory and a slave computing device having a slave device memory, and the slave computing device is coupled to the host computing device through a data bus to exchanged data therewith; and the method comprises: storing, for each of one or more processing processes, a system memory page table representing mapping relationships between virtual addresses and system physical addresses in the host device memory, wherein the system physical addresses comprise host device physical addresses for addressing and accessing respective host storage units in the host device memory and slave device physical addresses for addressing and accessing respective slave storage units in the slave device memory; converting requested virtual addresses into host device physical addresses or slave device physical addresses based on the system memory page table by a host address mapping management unit of the host computing device in response to a data access request of a processing process of the processing processes running on the host computing device, to allow the host computing device to access corresponding host storage units or slave storage units; storing a slave device memory page table in the slave device memory, wherein the slave device memory page table comprises at least a part of the system memory page table which comprises mapping relationships between virtual addresses and system physical addresses that are requested and received by the slave computing device from the host computing device according to a data access request of a processing process of the processing processes running on the slave computing device, wherein the mapping relationships are used for the processing process running on the slave computing device, and the slave device memory page table comprises mapping relationships between virtual addresses of data r

Assignees

Inventors

Classifications

  • G06F3/0644Primary

    Management of space entities, e.g. partitions, extents, pools · CPC title

  • Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators · CPC title

  • User address space allocation, e.g. contiguous or non contiguous base addressing · CPC title

  • using page tables, e.g. page table structures · CPC title

  • Plurality of storage devices · CPC title

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Frequently asked questions

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What does patent US11656779B2 cover?
A computing system includes a host computing device and a slave computing device. The host computing device comprises a host processor, a host device memory and a host address mapping management. The host address mapping management manages a system memory page table, and converts, in response to a data access request from a processing process run on the host processor, requested virtual address…
Who is the assignee on this patent?
Montage Technology Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F3/0644. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue May 23 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).