High-speed signal subsystem testing system

Patent metadata

Field	Value
Publication number	US-11656264-B2
Application number	US-202117374119-A
Country	US
Kind code	B2
Filing date	Jul 13, 2021
Priority date	Jul 13, 2021
Publication date	May 23, 2023
Grant date	May 23, 2023

Abstract

A high-speed signal subsystem testing system includes a processing system having a transmitter and a receiver, a loop back subsystem coupled to the transmitter and receiver to provide a testing communication path between the transmitter and the receiver, and a communication path testing engine coupled to the transmitter and the receiver. The communication path testing engine generates test signal(s) and transmits the test signal(s) via the transmitter and through the testing communication path provided by the loop back subsystem and, in response, receives test signal result(s) via the receiver and through the testing communication path provided by the loop back subsystem, The communication path testing engine processes the test signal result(s) to generate a testing impedance profile for the testing communication path, and compares the testing impedance profile to an expected impedance profile to determine whether a testing communication path issue exists in the testing communication path.

First claim

What is claimed is:

1. A high-speed signal subsystem testing system, comprising:
a processing system having a transmitter and a receiver;
a loop back subsystem coupled to each of the transmitter and the receiver to provide a testing communication path between the transmitter and the receiver that includes a plurality of different testing communication path portions; and
a communication path testing engine that is coupled to the transmitter and the receiver, wherein the communication path testing engine is configured to:
generate at least one test signal and transmit the at least one test signal via the transmitter and through the testing communication path provided by the loop back subsystem;
receive, in response to transmitting the at least one test signal, at least one test signal result via the receiver and through the testing communication path provided by the loop back subsystem;
process the at least one test signal result to generate a testing impedance profile for the testing communication path that identifies a varying impedance across the plurality of different testing communication path portions included in the testing communication path;
compare the testing impedance profile for the testing communication path to an expected impedance profile and determine that at least one testing communication path issue exists in any of the plurality of different testing communication path portions included in the testing communication path; and
generate and transmit, in response to determining that the at least one testing communication path issue exists in any of the plurality of different testing communication path portions included in the testing communication path, a testing communication path issue communication.

2. The system of claim 1 , wherein the at least one test signal is provided by at least one step function and the at least one test signal result is provided by at least one reflection.

3. The system of claim 2 , wherein the at least one test signal is at least one Time-Domain Reflectometer (TDR) test signal and the at least one test signal result is at least one TDR reflection.

4. The system of claim 1 , wherein the processing of the at least one test signal result to generate the testing impedance profile for the testing communication path includes performing a Fast Fourier Transform (FFT) on the at least one test signal result to generate a transfer function, and generating the testing impedance profile for the testing communication path based on the transfer function.

5. The system of claim 1 , wherein the plurality of different testing communication path portions included in the testing communication path provided between the transmitter and the receiver by the loop back subsystem includes at least one processing system mounting element portion, at least one circuit board trace portion, at least one connector portion, and at least one cable portion.

6. The system of claim 1 , wherein the testing communication path issue includes at least one of a processing system mounting element issue, a circuit board trace issue, a connector issue, or a cable issue.

7. The system of claim 1 , wherein the communication path testing engine is configured to:
generate the expected impedance profile using an expected communication path in which no testing communication path issues exist.

8. An Information Handling System (IHS), comprising:
a processing system; and
a memory system that is coupled to the processing system and that includes instructions that, when executed by the processing system, cause the processing system to provide a communication path testing engine that is configured to:
generate at least one test signal and transmit the at least one test signal via a transmitter and through a testing communication path that is provided by a loop back subsystem between the transmitter and a receiver and that includes a plurality of different testing communication path portions;
receive, in response to transmitting the at least one test signal, at least one test signal result via the receiver and through the testing communication path that is provided by the loop back subsystem between the transmitter and the receiver and that includes a plurality of different testing communication path portions;
process the at least one test signal result to generate a testing impedance profile for the testing communication path that identifies a varying impedance across the plurality of different testing communication path portions included in the testing communication path;
compare the testing impedance profile for the testing communication path to an expected impedance profile to determine whether a testing communication path issue exists in any of the plurality of different testing communication path portions included in the testing communication path; and
generate and transmit, in response to determining that the at least one testing communication path issue exists in any of the plurality of different testing communication path portions included in the testing communication path, a testing communication path issue communication.

9. The IHS of claim 8 , wherein the at least one test signal is provided by at least one Time-Domain Reflectometer (TDR) step function and the at least one test signal result is provided by at least one TDR reflection.

10. The IHS of claim 8 , wherein the processing of the at least one test signal result to generate the testing impedance profile for the testing communication path includes performing a Fast Fourier Transform (FFT) on the at least one test signal result to generate a transfer function, and generating the testing impedance profile for the testing communication path based on the transfer function.

11. The IHS of claim 8 , wherein the plurality of different testing communication path portions included in the testing communication path provided between the transmitter and the receiver by the loop back subsystem includes at least one processing system mounting element portion, at least one circuit board trace portion, at least one connector portion, and at least one cable portion.

12. The IHS of claim 8 , wherein the testing communication path issue includes at least one of a processing system mounting element issue, a circuit board trace issue, a connector issue, or a cable issue.

13. The IHS of claim 7 , wherein the communication path testing engine is configured to:
generate the expected impedance profile using an expected communication path in which no testing communication path issues exist.

14. A method for testing high-speed signaling subsystem, comprising:
generating, by a communication path testing subsystem, at least one test signal;
transmitting, by the communication path testing subsystem, the at least one test signal via a transmitter and through a testing communication path that is provided by a loop back subsystem between the transmitter and a receiver and that includes a plurality of different testing communication path portions;
receiving, by the communication path testing subsystem in response to transmitting the at least one test signal, at least one test signal result via the receiver and through the testing communication path that is provided by the loop back subsystem between the transmitter and the receiver and that includes a plurality of different testing communication path portions;
processing, by the communication path testing subsystem, the at least one test signal result to generate a testing impedance profile for the testing communication path that identifies a varying impedance across the plurality of different testing communication path portions included in the testin

Assignees

• Dell Products Lp

Inventors

• Chandra Umesh
• Mutnury Bhyrav

Classifications

• H04B3/46 Primary

  Monitoring; Testing · CPC title

• G01R31/68

  Testing of releasable connections, e.g. of terminals mounted on a printed circuit board · CPC title

• G06F17/142

  Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm · CPC title

• G01R31/31716

  Testing of input or output with loop-back · CPC title

• G01R31/083

  in cables, e.g. underground · CPC title