4F2 DRAM cell using vertical thin film transistor

Patent metadata

Field	Value
Publication number	US-11653487-B2
Application number	US-201816013798-A
Country	US
Kind code	B2
Filing date	Jun 20, 2018
Priority date	Jun 20, 2018
Publication date	May 16, 2023
Grant date	May 16, 2023

Abstract

Embodiments include a transistor device that comprises a gate electrode and a gate dielectric surrounding the gate electrode. In an embodiment, a source region may be below the gate electrode and a drain region may be above the gate electrode. In an embodiment, a channel region may be between the source region and the drain region. In an embodiment, the channel region is separated from a sidewall of the gate electrode by the gate dielectric. In an embodiment, a capacitor may be electrically coupled to the drain region.

First claim

What is claimed is:

1. A transistor device, comprising:
a gate electrode;
a gate dielectric surrounding the gate electrode;
a semiconductor layer, the semiconductor layer continuous from a location above a top of the gate electrode that vertically overlaps with the top of the gate electrode, along sidewalls of the gate electrode, and to a location below a bottom of the gate electrode that vertically overlaps with the bottom of the gate electrode;
a source region below the gate electrode;
a drain region above the gate electrode;
a channel region between the source region and the drain region, wherein the channel region is separated from a sidewall of the gate electrode by the gate dielectric, and wherein at least a portion of the channel region is in the semiconductor layer; and
a capacitor electrically coupled to the drain region.

2. The transistor device of claim 1 , wherein the capacitor is comprises an interdigitated interface between a capacitor storage node and top electrode.

3. The transistor device of claim 1 , wherein the gate dielectric has a non-uniform thickness around the gate electrode.

4. The transistor device of claim 3 , wherein a thickness of the gate dielectric below the gate electrode is greater than a thickness of the gate dielectric above the gate electrode.

5. The transistor device of claim 1 , wherein a thickness of the source region is greater than a thickness of the drain region.

6. The transistor device of claim 1 , wherein a surface of the channel opposite the gate dielectric is in contact with sealant layer.

7. The transistor device of claim 6 , wherein the sealant layer is a bilayer.

8. The transistor device of claim 1 , wherein the gate electrode comprises a stack of conductive materials.

9. The transistor device of claim 1 , wherein the gate dielectric comprises a multi-layer stack.

10. The transistor device of claim 1 , wherein the transistor device is in one or more interlayer dielectric (ILD) layers over a semiconductor substrate.

11. The transistor device of claim 1 , wherein the semiconductor semiconductive layer comprises an oxide semiconductor material.

12. The transistor device of claim 1 , wherein the semiconductor layer comprises a III-V material.

Assignees

• Intel Corp

Inventors

• Sharma Abhishek
• Wang Yih

Classifications

• H10D30/6704

  having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device · CPC title

• H10D30/674

  characterised by the active materials · CPC title

• H10D30/6728 Primary

  Vertical TFTs · CPC title

• H10D30/673

  characterised by the shapes, relative sizes or dispositions of the gate electrodes · CPC title

• H10D30/6736

  characterised by the shape of gate insulators · CPC title