Microchip for driving a resonant circuit

Patent metadata

Field	Value
Publication number	US-11653152-B1
Application number	US-202217877848-A
Country	US
Kind code	B1
Filing date	Jul 29, 2022
Priority date	Dec 15, 2021
Publication date	May 16, 2023
Grant date	May 16, 2023

Abstract

A microchip (300) for driving a resonant circuit, wherein the resonant circuit is an inductance (L) capacitance (C) circuit (LC tank), an antenna or a piezoelectric transducer, and wherein the microchip (300) is a single unit which includes a plurality of interconnected embedded components and subsystems including at least an oscillator (315), a pulse width modulation (PWM) signal generator subsystem (329), an analogue to digital converter (ADC) subsystem (318) and a digital to analogue converter (DAC) subsystem (327).

First claim

The invention claimed is:

1. A microchip for driving a resonant circuit, wherein the resonant circuit is an LC tank, an antenna or a piezoelectric transducer, and wherein the microchip is a single unit which comprises a plurality of interconnected embedded components and subsystems comprising:
an oscillator which generates:
a main clock signal,
a first phase clock signal which is high for a first time during a positive half-period of the main clock signal and low during a negative half-period of the main clock signal, and
a second phase clock signal which is high for a second time during the negative half-period of the main clock signal and low during the positive half-period of the main clock signal, wherein phases of the first phase clock signal and the second phase clock signal are centre aligned;

a pulse width modulation (PWM) signal generator subsystem which generates a two phase centre aligned PWM signal, the PWM signal generator subsystem comprising:
a delay locked loop which generates a double frequency clock signal using the first phase clock signal and the second phase clock signal, the double frequency clock signal being double a frequency of the main clock signal, wherein the delay locked loop controls a rising edge of the first phase clock signal and the second phase clock signal to be synchronous with a rising edge of the double frequency clock signal, and wherein the delay locked loop adjusts a frequency and a duty cycle of the first phase clock signal and the second phase clock signal in response to a driver control signal to produce a first phase output signal and a second phase output signal of the two phase centre aligned PWM signal, wherein the first phase output signal and the second phase output signal of the two phase centre aligned PWM signal are configured to drive an H-bridge circuit to generate an AC drive signal to drive the resonant circuit;
a first phase output signal terminal which outputs the first phase output signal to the H-bridge circuit;
a second phase output signal terminal which outputs the second phase output signal to the H-bridge circuit;
a feedback input terminal which receives a feedback signal from the H-bridge circuit;

an analogue to digital converter (ADC) subsystem comprising:
a plurality of ADC input terminals which receive a plurality of respective analogue signals, wherein one ADC input terminal of the plurality of ADC input terminals is connected to the feedback input terminal such that the ADC subsystem receives the feedback signal from the H-bridge circuit, and wherein the ADC subsystem samples analogue signals received at the plurality of ADC input terminals at a sampling frequency which is proportional to the frequency of the main clock signal and the ADC subsystem generates ADC digital signals using sampled versions of the analogue signals;
a digital processor subsystem which receives the ADC digital signals from the ADC subsystem and processes the ADC digital signals to generate the driver control signal, wherein the digital processor subsystem communicates the driver control signal to the PWM signal generator subsystem to control the PWM signal generator subsystem; and
a digital to analogue converter (DAC) subsystem comprising:
a digital to analogue converter (DAC) which converts a digital control signal generated by the digital processor subsystem into an analogue voltage control signal to control a voltage regulator circuit which generates a voltage for modulation by the H-bridge circuit; and
a DAC output terminal which outputs the analogue voltage control signal to control the voltage regulator circuit to generate a predetermined voltage for modulation by the H-bridge circuit to drive the resonant circuit in response to feedback signals which are indicative of an operation of the resonant circuit.

2. The microchip of claim 1 , wherein the oscillator generates the main clock signal at a frequency of 50 kHz to 105 MHz.

3. The microchip of claim 1 , wherein the microchip further comprises:
a frequency divider which is connected to the oscillator to receive the main clock signal from the oscillator, the frequency divider dividing the main clock signal by a predetermined divisor amount and outputting a frequency reference signal to the delay locked loop.

4. The microchip of claim 1 , wherein the delay locked loop comprises a plurality of delay lines connected end to end, wherein a total delay of the plurality of delay lines is equal to a period of the main clock signal.

5. The microchip of claim 4 , wherein the delay locked loop adjusts the duty cycle of the first phase clock signal and the second phase clock signal in response to the driver control signal by varying a delay of each of the plurality of delay lines in the delay locked loop.

6. The microchip of claim 1 , wherein the feedback input terminal receives a feedback signal which is indicative of a parameter of operation of the H-bridge circuit or AC drive signal when the H-bridge circuit is driving the resonant circuit with the AC drive signal.

7. The microchip of claim 1 , wherein the feedback input terminal receives a feedback signal from the H-bridge circuit in a form of a voltage which indicative of an rms current of an AC drive signal which is driving the resonant circuit.

8. The microchip of claim 1 , wherein the ADC subsystem comprises a plurality of further ADC input terminals which receive feedback signals which are indicative of at least one of a voltage of a battery connected to the microchip or the voltage of a battery charger connected to the microchip.

9. The microchip of claim 1 , wherein the microchip further comprises:
a temperature sensor which is embedded within the microchip, wherein the temperature sensor generates a temperature signal which is indicative of a temperature of the microchip, and wherein the temperature signal is received by a further ADC input terminal of the ADC subsystem and the temperature signal is sampled by the ADC subsystem.

10. The microchip of claim 1 , wherein the ADC subsystem samples signals received at the plurality of ADC input terminals sequentially with each signal being sampled by the ADC subsystem a respective predetermined number of times.

11. The microchip of claim 1 , wherein the microchip further comprises:
a battery charging subsystem which controls charging of an external battery which is connected to the microchip.

12. The microchip of claim 1 , wherein the DAC subsystem comprises:
a further digital to analogue converter (DAC) which converts a further digital control signal generated by the digital processor subsystem into a further analogue voltage control signal to control the voltage regulator circuit.

13. A microchip for driving a resonant circuit, wherein the resonant circuit is an LC tank, an antenna or a piezoelectric transducer, and wherein the microchip is a single unit which comprises a plurality of interconnected embedded components and subsystems comprising:
an oscillator which generates:
a main clock signal,
a first phase clock signal which is high for a first time during a positive half-period of the main clock signal and low during a negative half-period of the main clock signal, and
a second phase clock signal which is high for a second time during the negative half-period of the main clock signal and low during the positive half-period of the main clock signal, wherein phases of the first phase clock signal and the second phase clock signal are centre aligned;

a pulse width modulation (PWM) signal generator subsystem which generates a two phase centre aligned PWM signal, the PWM signal generator subsystem comprising:
a delay locked loop which

Assignees

• Shaheen Innovations Holding Ltd

Inventors

• Lahoud Imad

Classifications

• H04R17/10 Primary

  Resonant transducers, i.e. adapted to produce maximum output at a predetermined frequency · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• B06B1/0215 Primary

  for generating pulses, e.g. bursts of oscillations, envelopes · CPC title

• Y02B70/10

  Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title