Wideband power amplifier arrangement

Patent metadata

Field	Value
Publication number	US-11652452-B2
Application number	US-201716500923-A
Country	US
Kind code	B2
Filing date	Apr 6, 2017
Priority date	Apr 6, 2017
Publication date	May 16, 2023
Grant date	May 16, 2023

Abstract

A power amplifier arrangement ( 200 ) for amplifying an input signal to produce an output signal comprises a plurality N of amplifier sections ( 212, 213 ), a first input transmission line ( 221 ) comprising multiple segments and a first output transmission line ( 231 ) comprising multiple segments. Each amplifier section comprises one or more first transistors (T 1 ) distributed along the first input transmission line ( 221 ) and the first output transmission line ( 231 ). Each amplifier section is configured to amplify a portion of the input signal to produce a portion of the output signal. A portion of the input signal is one of N portions of the input signal partitioned on any one or a combination of an amplitude basis and a time basis. The output signal is produced at an end of the first output transmission line ( 231 ) by building up N potions of the output signal from each amplifier section.

First claim

The invention claimed is:

1. A power amplifier arrangement for amplifying an input signal to produce an output signal, the power amplifier arrangement comprising:
a plurality of N successive amplifier sections, wherein N is a positive integer that is greater than or equal to 2 and further wherein the plurality of N successive amplifier sections comprises a first amplifier section and a second amplifier section;
a first input transmission line comprising multiple segments; and
a first output transmission line comprising multiple segments, wherein
each of the N successive amplifier sections comprises one or more first transistors distributed along the first input transmission line and the first output transmission line such that gates of the one or more first transistors are connected to respective segments of the first input transmission line and drains of the one or more first transistors are connected to respective segments of the first output transmission line,
the first amplifier section is configured to amplify a first portion of the input signal, thereby producing a first portion of the output signal,
the first portion of the input signal is associated with a first amplitude range and/or a first time interval of the input signal,
the second amplifier section is configured to amplify a second portion of the input signal, which is different from the first portion of the input signal, thereby producing a second portion of the output signal,
the second portion of the input signal is associated with a second amplitude range and/or a second time interval of the input signal, and
the output signal is produced at an end of the first output transmission line by building up at least the first and second portions of the output signal,
each of the N successive amplifier sections further comprises one or more second transistors,
the power amplifier arrangement further comprises a second input transmission line comprising multiple segments and a second output transmission line comprising multiple segments,
gates of the one or more second transistors are connected to respective segments of the second input transmission line,
drains of the one or more second transistors are connected to respective segments of the second output transmission line, and
each of the N successive amplifier sections is configured to amplify a portion of positive input signal to produce a portion of positive output signal at the first output transmission line and to amplify a portion of negative input signal to produce a portion of negative output signal at the second output transmission line.

2. The power amplifier arrangement according to claim 1 , wherein the N portions of the input signal is partitioned by pre-shaping the N portions of the input signal by digital or analog shaping circuits before being input to each of the N successive amplifier sections.

3. The power amplifier arrangement according to claim 1 , wherein lengths of the respective segments of the first output transmission line are non-equal.

4. The power amplifier arrangement according to claim 1 , further comprising a wideband coupler to combine positive and negative output signals from the first and second output transmission lines.

5. The power amplifier arrangement according to claim 1 , wherein the one or more second transistors are the same type as the respective one or more first transistors and are connected in differential with the respective one or more first transistors.

6. The power amplifier arrangement according to claim 5 , further comprising a negatively coupled inductor pair or a center-tapped inductor to feed direct current (DC) to the differentially connected transistors.

7. The power amplifier arrangement according to claim 5 , further comprising a balun or balanced-to-unbalanced transformer or a wideband 180-degree coupler to combine positive and negative output signals from the first and second output transmission lines.

8. A power amplifier arrangement for amplifying an input signal to produce an output signal, the power amplifier arrangement comprising:
a plurality of N successive amplifier sections, wherein N is a positive integer that is greater than or equal to 2 and further wherein the plurality of N successive amplifier sections comprises a first amplifier section and a second amplifier section;
a first input transmission line comprising multiple segments; and
a first output transmission line comprising multiple segments, wherein
each of the N successive amplifier sections comprises one or more first transistors distributed along the first input transmission line and the first output transmission line such that gates of the one or more first transistors are connected to respective segments of the first input transmission line and drains of the one or more first transistors are connected to respective segments of the first output transmission line,
the first amplifier section is configured to amplify a first portion of the input signal, thereby producing a first portion of the output signal,
the first portion of the input signal is associated with a first amplitude range and/or a first time interval of the input signal,
the second amplifier section is configured to amplify a second portion of the input signal, which is different from the first portion of the input signal, thereby producing a second portion of the output signal,
the second portion of the input signal is associated with a second amplitude range and/or a second time interval of the input signal, and
the output signal is produced at an end of the first output transmission line by building up at least the first and second portions of the output signal,
each of the N successive amplifier sections further comprises one or more second transistors stacked with the respective one or more first transistors,
the power amplifier arrangement further comprises a second input transmission line comprising multiple segments,
gates of the one or more second transistors are connected to respective segments of the second input transmission line,
drains of the one or more second transistors are connected to respective segments of the first output transmission line, and
each of the N successive amplifier sections is configured to amplify a portion of positive input signal and a portion of negative input signal to produce a portion of positive output signal and a portion of negative output signal at the first output transmission line.

9. An electronic device comprising a power amplifier arrangement according to claim 1 .

10. The power amplifier arrangement according to claim 1 , wherein
the gates of the one or more second transistors are directly connected to the respective segments of the second input transmission line, and
the drains of the one or more second transistors are directly connected to the respective segments of the second output transmission line.

11. The power amplifier arrangement according to claim 1 , wherein the N successive amplifier sections are configured to divide the input signal into the N portions of the input signal.

12. The power amplifier arrangement according to claim 1 , wherein
the first amplifier section comprises a first number of transistors,
the second amplifier section comprises a second number of transistors, and
the first number and the second number are different.

13. A power amplifier arrangement for amplifying an input signal to produce an output signal, the power amplifier arrangement comprising:
a plurality of N successive amplifier sections, wherein N is a positive integer that is greater than or equal to 2 and further wherein the plurality of N successive amplifier secti

Assignees

• Ericsson Telefon Ab L M

Inventors

• Hellberg Richard

Classifications

• H03F2200/522

  the bias or supply voltage or current of the gate side of a FET amplifier being controlled to be on or off by a switch · CPC title

• H03F2200/432

  Two or more amplifiers of different type are coupled in parallel at the input or output, e.g. a class D and a linear amplifier, a class B and a class A amplifier · CPC title

• H03F1/0261

  with control of the polarisation voltage or current, e.g. gliding Class A · CPC title

• H03F3/301

  CMOS common drain output SEPP amplifiers (H03F3/3008 takes precedence) · CPC title

• H03F2200/516

  Some amplifier stages of an amplifier use supply voltages of different value · CPC title