Metal oxide film and method for forming metal oxide film

Patent metadata

Field	Value
Publication number	US-11652110-B2
Application number	US-202117144550-A
Country	US
Kind code	B2
Filing date	Jan 8, 2021
Priority date	Nov 8, 2012
Publication date	May 16, 2023
Grant date	May 16, 2023

Abstract

A metal oxide film including a crystal part and having highly stable physical properties is provided. The size of the crystal part is less than or equal to 10 nm, which allows the observation of circumferentially arranged spots in a nanobeam electron diffraction pattern of the cross section of the metal oxide film when the measurement area is greater than or equal to 5 nmφ and less than or equal to 10 nmφ.

First claim

The invention claimed is:

1. A display device comprising:
a display panel comprising a pixel, the pixel comprising:
a first transistor;
a second transistor;
a capacitor; and
a display element,

wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to a first wiring,
wherein an other of the source electrode and the drain electrode of the first transistor is electrically connected to a gate of the second transistor and a first electrode of the capacitor,
wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to a first electrode of the display element,
wherein an other of the source electrode and the drain electrode of the second transistor is electrically connected to a second wiring,
wherein one of the first transistor and the second transistor comprises:
a gate electrode over a substrate;
a first insulating layer over the gate electrode,
an oxide semiconductor layer comprising a channel over the first insulating layer;
the source electrode and the drain electrode electrically connected to the oxide semiconductor layer;
a second insulating layer over the oxide semiconductor layer; and
a third insulating layer over and in contact with the second insulating layer,

wherein the oxide semiconductor layer comprises indium, gallium, and zinc,
wherein the oxide semiconductor layer includes a crystalline portion in which a plurality of circumferentially distributed spots are observable in a nanobeam electron diffraction pattern of the oxide semiconductor layer, and
wherein a size of a crystal in the crystalline portion is larger than or equal to 1 nm and smaller than or equal to 10 nm.

2. The display device according to claim 1 , wherein a second electrode of the capacitor is electrically connected to the second wiring.

3. The display device according to claim 1 ,
wherein the crystalline portion includes a plurality of crystals, and
wherein surface orientations of the plurality of crystals are random.

4. The display device according to claim 1 , wherein the crystalline portion is included in the channel of the one of the first transistor and the second transistor.

5. The display device according to claim 1 , wherein the plurality of circumferentially distributed spots are observable in a measurement area greater than or equal to an area with a diameter of 5 nmφ and less than or equal to an area with a diameter of 10 nmφ in the nanobeam electron diffraction pattern of a cross-section of the oxide semiconductor layer.

6. The display device according to claim 1 ,
wherein the oxide semiconductor layer has a first region between a pair of second regions, and
wherein the first region is smaller than the pair of second regions.

7. The display device according to claim 1 , wherein an atomic ratio of indium, gallium, and zinc in the oxide semiconductor layer is 1:1:1.

8. The display device according to claim 1 , wherein the gate electrode has a tapered side surface.

9. A display device comprising:
a display panel comprising a pixel, the pixel comprising:
a first transistor;
a second transistor;
a capacitor; and
a display element,

wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to a first wiring,
wherein an other of the source electrode and the drain electrode of the first transistor is electrically connected to a gate of the second transistor and a first electrode of the capacitor,
wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to a first electrode of the display element,
wherein an other of the source electrode and the drain electrode of the second transistor is electrically connected to a second wiring,
wherein one of the first transistor and the second transistor comprises:
a gate electrode over a glass substrate, the gate electrode comprising a first layer comprising molybdenum and a second layer comprising copper;
a first insulating layer over the gate electrode, the first insulating layer comprising a third layer comprising silicon nitride and a fourth layer comprising silicon oxide,
an oxide semiconductor layer comprising a channel over the first insulating layer;
the source electrode and the drain electrode electrically connected to the oxide semiconductor layer;
a second insulating layer over the oxide semiconductor layer, the second insulating layer comprising silicon oxide; and
a third insulating layer over and in contact with the second insulating layer,

wherein the oxide semiconductor layer comprises indium, gallium, and zinc,
wherein the oxide semiconductor layer includes a crystalline portion in which a plurality of circumferentially distributed spots are observable in a nanobeam electron diffraction pattern of the oxide semiconductor layer, and
wherein a size of a crystal in the crystalline portion is larger than or equal to 1 nm and smaller than or equal to 10 nm.

10. The display device according to claim 9 , wherein a second electrode of the capacitor is electrically connected to the second wiring.

11. The display device according to claim 9 ,
wherein the crystalline portion includes a plurality of crystals, and
wherein surface orientations of the plurality of crystals are random.

12. The display device according to claim 9 , wherein the crystalline portion is included in the channel of the one of the first transistor and the second transistor.

13. The display device according to claim 9 , wherein the plurality of circumferentially distributed spots are observable in a measurement area greater than or equal to an area with a diameter of 5 nmφ and less than or equal to an area with a diameter of 10 nmφ in the nanobeam electron diffraction pattern of a cross-section of the oxide semiconductor layer.

14. The display device according to claim 9 ,
wherein the oxide semiconductor layer has a first region between a pair of second regions, and
wherein the first region is smaller than the pair of second regions.

15. The display device according to claim 9 , wherein an atomic ratio of indium, gallium, and zinc in the oxide semiconductor layer is 1:1:1.

16. The display device according to claim 9 , wherein the gate electrode has a tapered side surface.

Assignees

• Semiconductor Energy Lab

Inventors

• Takahashi Masahiro
• Hirohashi Takuya
• Tsubuku Masashi
• Ishihara Noritaka
• Oota Masashi

Classifications

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10P14/3426 Primary

  Oxides · CPC title

• H10P14/2922

  being non-crystalline insulating materials, e.g. glass or polymers · CPC title

• H10P14/2901

  Materials · CPC title

• H10P14/22

  using physical deposition, e.g. vacuum deposition or sputtering · CPC title