Semiconductor substrate crack mitigation systems and related methods

Patent metadata

Field	Value
Publication number	US-11652010-B2
Application number	US-202117305624-A
Country	US
Kind code	B2
Filing date	Jul 12, 2021
Priority date	Apr 27, 2018
Publication date	May 16, 2023
Grant date	May 16, 2023

Abstract

Implementations of a method for healing a crack in a semiconductor substrate may include identifying a crack in a semiconductor substrate and heating an area of the semiconductor substrate including the crack until the crack is healed.

First claim

What is claimed is:

1. A method for healing a crack in a semiconductor substrate, the method comprising:
identifying a crack in a semiconductor substrate;
heating an area of the semiconductor substrate comprising the crack until the crack is healed;
coupling the semiconductor substrate to a carrier substrate;
completing processing of the semiconductor substrate while coupled to the carrier substrate; and
forming a plurality of semiconductor die therefrom.

2. The method of claim 1 , wherein the semiconductor substrate comprises silicon carbide.

3. The method of claim 1 , further comprising electronically identifying the area of the semiconductor substrate comprising the crack after the crack is healed.

4. The method of claim 1 , further comprising forming a same crystal orientation of the heated area of the semiconductor substrate as a remainder of the semiconductor substrate through one of controlled cooling, controlled heating, and controlled heating and controlled cooling of the heated area of the semiconductor substrate.

5. The method of claim 1 , further comprising forming a different crystal orientation of the heated area of the semiconductor substrate as a remainder of the semiconductor substrate through one of controlled cooling, controlled heating, and controlled heating and controlled cooling of the heated area of the semiconductor substrate.

6. The method of claim 1 , wherein a laser is used to heat an area of the semiconductor substrate.

7. The method of claim 1 , further comprising electronically identifying the area of the semiconductor substrate comprising the crack and only heating substantially the area of the semiconductor substrate electronically identified.

8. The method of claim 1 , wherein heating the area of the semiconductor substrate comprising the crack until the crack is healed comprises localized heating of the area of the semiconductor substrate comprising the crack until the crack is healed.

9. The method of claim 1 , wherein heating the area of the semiconductor substrate comprising the crack until the crack is healed comprises heating the entire semiconductor substrate.

10. The method of claim 1 , wherein the crack extends to an edge of the semiconductor substrate.

11. The method of claim 1 , wherein the crack is an internal crack.

12. A method for mitigating propagation of a crack in a semiconductor substrate, the method comprising:
identifying a crack in a semiconductor substrate;
removing a portion of the semiconductor substrate comprising the crack;
forming a filled area by filling, with a fill material, an area of the semiconductor substrate from where the portion of the semiconductor substrate comprising the crack was removed;
electronically identifying the filled area; and
forming a plurality of semiconductor die from the semiconductor substrate excluding the filled area.

13. The method of claim 12 , wherein the semiconductor substrate comprises silicon carbide.

14. The method of claim 12 , wherein removing a portion of the semiconductor substrate comprises etching the portion of the semiconductor substrate.

15. The method of claim 12 , wherein removing a portion of the semiconductor substrate comprises polishing a sidewall of the semiconductor substrate.

16. The method of claim 12 , further comprising coupling the semiconductor substrate to a carrier substrate.

17. The method of claim 12 , wherein the crack extends to an edge of the semiconductor substrate.

18. The method of claim 12 , wherein the crack is an internal crack.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Seddon Michael J

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10W42/00

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10W46/401

  for identification or tracking · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10W42/121

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title