Multiple name space test systems and methods

Patent metadata

Field	Value
Publication number	US-11650893-B2
Application number	US-202117193668-A
Country	US
Kind code	B2
Filing date	Mar 5, 2021
Priority date	Mar 31, 2020
Publication date	May 16, 2023
Grant date	May 16, 2023

Abstract

Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a multiple-name-space testing system comprises a load board, testing electronics, and a namespace testing tracker. The load board is configured to couple with a plurality of devices under test (DUTs). The testing electronics are configured to test the plurality of DUTs, wherein the testing electronics are coupled to the load board. The controller is configured to direct testing of multiple-name-spaces across the plurality of DUTs at least in part in parallel. The controller can be coupled to the testing electronics. The namespace testing tracker is configured to track testing of the plurality of DUTs, including the testing of the multiple-name-spaces across the plurality of DUTs at least in part in parallel. In one embodiment, the DUTs are NVMe SSD devices.

First claim

What is claimed is:

1. A multiple-name-space testing system comprising:
a load board configured to couple with a plurality of devices under test (DUTs);
test electronics configured to test the plurality of DUTs, wherein the test electronics are coupled to the load board;
a controller configured to direct testing of multiple-name-spaces across the plurality of DUTs at least in part in parallel, wherein the multiple-name-spaces are located in the plurality of DUTs and wherein the controller is coupled to the testing electronics, wherein the multiple-name-spaces are located in the plurality of DUTs and wherein persistent namespace resources are pre-allocated for activation as part of a power up and deactivation as part of power down respectively for the plurality of DUTs, and wherein the controller handles user introduced testing requirements, including indicating that a first namespace is to be tested with full field programmable gate array (FPGA) hardware acceleration and indicating s second namespace is to be tested normally; and
a namespace testing tracker configured to track testing of the plurality of DUTs, including the testing of the multiple-name-spaces across the plurality of DUTs at least in part in parallel.

2. A multiple-name-space testing system of claim 1 wherein the plurality of DUTs are Non-Volatile Memory Express (NVMe) solid state drive (SSD) devices.

3. A multiple-name-space testing system of claim 1 wherein the controller directs sets of namespaces testing in parallel.

4. A multiple-name-space testing system of claim 1 , wherein multiple-name-spaces are tested in parallel across a plurality of devices.

5. A multiple-name-space testing system of claim 1 , wherein up to 128 devices are tested at least in part simultaneously.

6. A multiple-name-space testing system of claim 1 , wherein the namespace testing tracker can track and manage testing of multiple-name-spaces at a time per DUT.

7. A multiple-name-space testing system of claim 1 wherein the controller is configured to handle user introduced testing requirements that further complicate the tracking and management of the testing.

8. A multiple-name-space testing system comprising:
a load board configured to couple with a plurality of devices under test (DUTs);
test electronics configured to test the plurality of DUTs, wherein the test electronics are coupled to the load board;
a controller configured to direct testing of multiple-name-spaces across the plurality of DUTs at least in part in parallel, wherein directing the testing includes balancing interrupts from the plurality of DUTs based upon activities of the plurality of DUTs and number of processing cores available for testing operations, wherein the multiple-name-spaces are located in the plurality of DUTs and wherein persistent namespace resources are pre-allocated for activation as part of a power up and deactivation as part of power down respectively for the plurality of DUTs; and
a namespace testing tracker configured to track testing of the plurality of DUTs, including the testing of the multiple-name-spaces across the plurality of DUTs at least in part in parallel, wherein the namespace testing tracker includes intelligence configured to select namespaces for testing based on various factors, including characteristics of the namespaces and application of test features of test electronics.

9. A multiple-name-space testing method comprising:
configuring testing electronics to test the plurality of devices under test (DUTs), wherein the testing electronics are coupled to a load board;
directing testing of multiple-name-spaces across the plurality of DUTs at least in part in parallel, wherein the multiple-name-spaces are located in the plurality of DUTs, wherein the multiple-name-spaces are located in the plurality of DUTs and wherein persistent namespace resources are pre-allocated for activation as part of a power up and deactivation as part of power down respectively for the plurality of DUTs; and
tracking testing of the plurality of DUTs, including the testing of the multiple-name-spaces across the plurality of DUTs at least in part in parallel, wherein the tracking includes intelligence configured to select namespaces for testing based on various factors, including characteristics of the namespaces and application of test features of test electronics.

10. The multiple-name-space testing method of claim 9 , wherein the plurality of DUTs are NVMe SSD devices.

11. The multiple-name-space testing method of claim 9 , further comprising handling user introduced testing requirements, including indicating that a namespace is to be tested with full FPGA hardware acceleration while another namespace is tested normally.

12. The multiple-name-space testing method of claim 9 , wherein the directing includes testing control based on differences in namespace characteristics.

13. The multiple-name-space testing method of claim 9 , wherein the directing includes control for differences in sector size.

14. The multiple-name-space testing method of claim 9 wherein the directing includes control for differences in protection information.

15. A multiple-name-space testing system of claim 9 , wherein the directing includes directing sets of namespaces testing in parallel.

16. A multiple-name-space testing system of claim 9 , wherein multiple-name-spaces are tested in parallel across a plurality of devices.

17. A multiple-name-space testing system of claim 9 , wherein overall test time is compressed.

18. A multiple-name-space testing system of claim 9 , wherein directing includes application of test features of the test electronics to the plurality of DUTs.

19. A multiple-name-space testing system of claim 9 , further comprising handling user introduced testing requirements that further complicate the tracking and management of the testing.

Assignees

• Advantest Corp

Inventors

• Malisic Srdjan
• Yuan Chi

Classifications

• G11C2029/2602

  Concurrent test · CPC title

• G06F12/0238

  Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory · CPC title

• G11C2029/5602

  Interface to device under test · CPC title

• G06F11/2273

  Test methods · CPC title

• G06F2212/202

  Non-volatile memory · CPC title