Detecting address errors

Patent metadata

Field	Value
Publication number	US-11650877-B2
Application number	US-202016881473-A
Country	US
Kind code	B2
Filing date	May 22, 2020
Priority date	Mar 24, 2019
Publication date	May 16, 2023
Grant date	May 16, 2023

Abstract

A method for detecting an address error when reading a bitstream from a memory is proposed, wherein a check is carried out as to whether the bitstream in conjunction with the present read address is a code word of an error code and wherein, should the bitstream in conjunction with the present read address not be a code word of the error code, an address error is subsequently detected provided the error code does not correct an error correctable thereby. Accordingly, an apparatus, a system and a computer program product are specified.

First claim

The invention claimed is:

1. A method for detecting an address error when reading a bitstream from a memory, comprising:
checking whether the bitstream combined with a transformation of a present read address is a code word of an error code,
when the bitstream combined with the transformation of the present read address is not a code word of the error code, detecting and/or correcting an address error; and
detecting and/or correcting a memory cell error in the bitstream, when present, using the error code when the present read address is a code word of the error code.

2. The method as claimed in claim 1 , wherein the memory cell error to be corrected by the error code is a subset of the errors correctable by the error code.

3. The method as claimed in claim 1 , wherein no address error is detected if the bitstream combined with the transformation of the present read address is a code word of the error code.

4. The method as claimed in claim 1 , wherein the memory cell error is detected and/or corrected using a first error syndrome.

5. The method as claimed in claim 4 , wherein the address error is detected using a second error syndrome, the first error syndrome differing from the second error syndrome.

6. The method as claimed in claim 1 , wherein, before reading the bitstream from the memory, performing the following acts to represent the bitstream combined with the transformation of the present read address:
storing a bitstream vat an address a in the memory, the bitstream v and an address value f(a) transformed by means of a transformation f representing a code word of the error code, and
assigning the used memory address a to the transformed address value f(a)=A 1 , . . . , A m , where the transformed address value f(a) is different from an error syndrome of the memory cell error and different from values arising from error syndromes assigned to bit errors.

7. The method as claimed in claim 6 , wherein not all addresses of the memory are used.

8. The method as claimed in claim 1 , wherein the memory has memory cells, in which n-component bitstreams are storable, wherein N different bit errors b 1 to b N , which falsify a bitstream v=v 1 , . . . , vn into bitstreams v(b 1 ), v(b 2 ), . . . , V(b N ), are correctable, wherein a memory cell error φ 1 , in which n memory cells yield the values φ 1 1 , . . . , φ n 1 =φ 1 upon readout from the memory cells, is detected,
determining the bitstream v, which is written into the memory at an address a, such that in an error-free case is a code word of the error code Ca with an H-matrix H=(H m,n v ,I m ), and
determining an address transformation f such that it uniquely assigns a transformed address value f(a)=A 1 , . . . , A m , to each used memory address a, which transformed address value is not equal to the values
H m,n v ·φ 1 ,H m,n v ·φ 1 +s ( b 1 ), . . . , H m,n v ·φ 1 +s ( b N )

where s(bi) to s(bN) are error syndromes assigned to the bit errors, wherein the following relationships apply:
2 m >N+ 1 ,n≥ 2 ,m≥ 2 ,N≥ 1

where H m,n v denotes a binary (m,n)-matrix and in, denotes the m-dimensional unit matrix, and
wherein the combination of the bitstream v and the transformed address value f(a) is the combination of the bitstream and the transformation of the present read address.

9. The method as claimed in claim 8 , wherein a further memory cell error φ 2 is detected, where n memory cells addressed at one address yield the values φ 1 2 , . . . , φ n 2 =φ 2 when reading from the memory cells, and the address transformation f is determined in such a way that the transformed address value f(a) for each used memory address a is not equal to the values
H v ·φ 2 ,H v ·φ 2 +s ( b 1 ), . . . , H v ·φ 2 +s ( b N ).

10. The method as claimed in claim 8 , wherein the matrix H m,n v is an H-matrix of a Hamming code or a shortened Hamming code.

11. The method as claimed in claim 8 , wherein the matrix H m,n v is an H-matrix of a Hsiao code or a shortened Hsiao code.

12. The method as claimed in claim 8 , wherein the matrix H m,n v is an H-matrix of a t bit error correcting code.

13. The method as claimed in claim 8 , wherein the matrix H m,n v is an H-matrix of a BCH code.

14. The method as claimed in claim 8 , wherein, for the purposes of increasing the probability of detecting an address error, the-H-matrix
H =[ H m,n v ,I m ]

of an error code is changed into a modified H-matrix
H =[ H m+1,n v ,I m+1 ]

by virtue of an (m+1)-th row of n binary values being added to the matrix H m,n v .

15. The method as claimed in claim 14 , wherein the (m+1)-th row, which is added to the matrix H m,n v , comprises n zeros.

16. An apparatus for detecting an address error, wherein the apparatus comprises:
a processing unit to:
check whether a bitstream combined with a transformation of a present read address is a code word of an error code, and
when the bitstream combined with the transformation of the present read address is not a code word of the error code, detect and/or correct an address error.

17. The apparatus as claimed in claim 16 , wherein the processing unit is configured to read the bitstream from a memory.

18. The apparatus of claim 16 , further comprising detecting and/or correcting a memory cell error in the bitstream, when present, using the error code when the present read address is a code word of the error code.

19. A non-transitory computer program product which is directly loadable into a memory of a digital computer, comprising program code parts suitable for performing acts of a method, comprising:
checking whether a bitstream combined with a transformation of a present read address is a code word of an error code,
when the bitstream combined with the transformation of the present read address is not a code word of the error code, detecting and/or correcting an address error, and
detecting and/or correcting a memory cell error in the bitstream, when present, using the error code when the present read address is a code word of the error code.

Assignees

• Infineon Technologies Ag

Inventors

• Kern Thomas
• Oberlaender Klaus
• Badack Christian
• Goessel Michael

Classifications

• H03M13/19

  Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes · CPC title

• H03M13/618

  Shortening and extension of codes · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• H03M13/1174

  Parity-check or generator matrices built from sub-matrices representing known block codes such as, e.g. Hamming codes, e.g. generalized LDPC codes · CPC title

• G06F11/3037

  where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00) · CPC title