Methods and apparatus to improve computing device power management

Patent metadata

Field	Value
Publication number	US-11650648-B2
Application number	US-202016914029-A
Country	US
Kind code	B2
Filing date	Jun 26, 2020
Priority date	Jun 26, 2020
Publication date	May 16, 2023
Grant date	May 16, 2023

Abstract

Methods, apparatus, systems, and articles of manufacture are disclosed to improve computing device power management. An example apparatus includes a usage classifier to classify usage of a computing system, a low battery probability determiner to determine a probability of the computing system operating with a low battery capacity based on the classification, a policy reward determiner to determine an adjustment of a policy based on at least one of the classification or the probability, and determine a battery capacity of the computing system in response to the adjustment, and a policy adjustor to adjust the policy in response to the battery capacity satisfying a threshold.

First claim

What is claimed is:

1. An apparatus for device power management, the apparatus comprising:
interface circuitry to obtain data from an electronic system;
machine readable instructions; and
processor circuitry to execute the machine readable instructions to:
determine a probability that the electronic system is to operate with a low battery power level based on a classification of usage of the electronic system;
determine an adjustment from a first active performance state to a second active performance state to increase performance of the electronic system;
determine, based on the probability not satisfying a threshold, that the electronic system is to be charged before a future battery power level of the electronic system falls beneath a battery power level below which the electronic system turns off, the future battery power level to occur in response to the adjustment; and
make the adjustment from the first active performance state to the second active performance state to cause at least one of an increase of a first frequency associated with a first hardware resource of the electronic system, an increase of a second frequency associated with a software resource of the electronic system, or an increase of power delivery to the first hardware resource or a second hardware resource of the electronic system, the at least one of the increase of the first frequency, the increase of the second frequency, or the increase of the power delivery to the first hardware resource or the second hardware resource to increase the performance of the electronic system.

2. The apparatus of claim 1 , wherein the data is telemetry data, and the interface circuitry is to determine a telemetry parameter based on the telemetry data from the electronic system, the telemetry parameter based on at least one of a location, a process, a power transition event, or a power source associated with the electronic system.

3. The apparatus of claim 1 , wherein the processor circuitry is to adjust a first policy to a second policy based on the adjustment, the second policy to improve the performance of the electronic system, the first policy to improve energy efficiency of the electronic system.

4. The apparatus of claim 1 , wherein the battery power level is a first battery power level, and the processor circuitry is to adjust a first policy to a second policy after a first determination that the probability satisfies the threshold and a second determination that the future battery power level will fall beneath a second battery power level, the second policy to improve energy efficiency of the electronic system, the first policy to improve the performance of the electronic system.

5. The apparatus of claim 1 , wherein the second hardware resource is an antenna, and the processor circuitry is to make the adjustment to cause at least one of an increase of a third frequency associated with the antenna, the increase of the second frequency associated with the software resource, or an increase of the power delivery to the first hardware resource or the antenna, the software resource to control operation of at least one of the first hardware resource or the antenna.

6. The apparatus of claim 1 , wherein the first active performance state is associated with a first energy expenditure, the first energy expenditure is less than a second energy expenditure associated with the second active performance state.

7. The apparatus of claim 1 , wherein the processor circuitry is to determine the future battery power level based on an operation of the electronic system in response to the adjustment.

8. The apparatus of claim 1 , wherein the processor circuitry is to determine that the electronic system is to be charged before the future battery power level of the electronic system falls beneath the battery power level based on a determination that the classification of the usage is associated with a user that has high low-battery anxiety, the user with high low battery anxiety unlikely to wait until the future battery power level falls beneath the battery power level before charging the electronic system.

9. A non-transitory computer readable storage device comprising instructions that, when executed, cause processor circuitry to at least:
determine a probability that an electronic system is to operate with a low battery charge based on a classification of usage of the electronic system;
determine an adjustment from a first active performance state to a second active performance state to increase performance of the electronic system;
determine, based on the probability not satisfying a threshold, that the electronic system is to be charged before a future battery charge of the electronic system falls beneath a battery charge at which the electronic system shuts down, the future battery charge to occur in response to the adjustment; and
cause the adjustment from the first active performance state to the second active performance state to cause at least one of an increase of a first frequency associated with a first hardware resource of the electronic system, an increase of a second frequency associated with a software resource of the electronic system, or an increase of power delivery to the first hardware resource or a second hardware resource of the electronic system.

10. The non-transitory computer readable storage device of claim 9 , wherein the instructions, when executed, cause the processor circuitry to determine a telemetry parameter based on telemetry data from the electronic system, the telemetry parameter based on at least one of a location, a process, a power transition event, or a power source associated with the electronic system.

11. The non-transitory computer readable storage device of claim 9 , wherein the instructions, when executed, cause the processor circuitry to change a first policy to a second policy based on the adjustment, the second policy to improve the performance of the electronic system, the first policy to improve energy efficiency of the electronic system.

12. The non-transitory computer readable storage device of claim 9 , wherein the battery charge is a first battery charge, and the instructions, when executed, cause the processor circuitry to change a first policy to a second policy after a first determination that the probability satisfies the threshold and a second determination that the future battery charge will fall beneath a second battery charge, the second policy to improve energy efficiency of the electronic system, the first policy to improve the performance of the electronic system.

13. The non-transitory computer readable storage device of claim 9 , wherein the second hardware resource is an antenna, and the instructions, when executed, cause the processor circuitry to cause the adjustment to cause at least one of an increase of a third frequency associated with the antenna, the increase of the second frequency associated with the software resource, or the increase of the power delivery to the antenna, the software resource to control operation of the antenna.

14. The non-transitory computer readable storage device of claim 9 , wherein the first active performance state is associated with a first energy expenditure less than a second energy expenditure associated with the second active performance state.

15. The non-transitory computer readable storage device of claim 9 , wherein the instructions, when executed, cause the processor circuitry to determine the future battery charge based on an operation of the electronic system in response to the adjustment.

16. The non-transitory computer readable storage dev

Assignees

• Intel Corp

Inventors

• Nge Chee Lim
• Domeika Maximilian
• Soe Soethiha
• Hermerding Ii James
• Wang Zhongsheng
• Elhefnawy Wessam
• Rotem Efraim
• Binns Christopher Joseph

Classifications

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F11/3072

  where the reporting involves data filtering, e.g. pattern matching, time or event triggered, adaptive or policy-based reporting · CPC title

• G06F1/3212 Primary

  Monitoring battery levels, e.g. power saving mode being initiated when battery voltage goes below a certain level · CPC title

• G06F11/3409

  for performance assessment · CPC title

• G06F11/3062

  where the monitored property is the power consumption (power management in a computing system G06F1/3203) · CPC title