Solid-state image pickup element, electronic equipment, and semiconductor apparatus

Patent metadata

Field	Value
Publication number	US-11647890-B2
Application number	US-202117445232-A
Country	US
Kind code	B2
Filing date	Aug 17, 2021
Priority date	Mar 3, 2017
Publication date	May 16, 2023
Grant date	May 16, 2023

Abstract

The present technology relates to a solid-state image pickup element, electronic equipment, and a semiconductor apparatus that make it possible to reduce a surface reflection in an area in which a slit is formed and improve flare characteristics. A solid-state image pickup element includes a pixel area in which a plurality of pixels is two-dimensionally arranged in a matrix, a chip mounting area in which a chip is flip-chip mounted, and a dam area that is arranged around the chip mounting area and in which one or more slits that block an outflow of a resin are formed. In the dam area, the same OCL as that in the pixel area is formed. The present technology can be applied to a solid-state image pickup element etc. in which a chip is flip-chip mounted, for example.

First claim

The invention claimed is:

1. A solid-state image pickup element, comprising:
a pixel area comprising a plurality of pixels arranged two-dimensionally in a matrix;
a chip mounting area in which a chip is flip-chip mounted; and
a dam area, around the chip mounting area, in which a plurality of slits is formed, wherein
the plurality of slits is configured to block an outflow of an underfill resin and an outflow of a light-shielding resin,
the plurality of slits comprises a first plurality of slits and a second plurality of slits,
a distance between the first plurality of slits and the pixel area is smaller than a distance between the second plurality of slits and the pixel area,
the first plurality of slits is configured to block the outflow of the light-shielding resin into the pixel area, and
the second plurality of slits is configured to block the outflow of the underfill resin into the pixel area.

2. The solid-state image pickup element according to claim 1 , wherein the light-shielding resin covers an upper surface and side surfaces of the chip.

3. The solid-state image pickup element according to claim 1 , wherein the underfill resin is filled in a range between the chip and a substrate on which the chip is flip-chip mounted.

4. The solid-state image pickup element according to claim 1 , wherein
the pixel area comprises at least one first on-chip lens (OCL), and
the dam area comprises at least one second OCL, and at least one third OCL.

5. The solid-state image pickup element according to claim 4 , wherein at least one slit of the plurality of slits is formed in the at least one third OCL.

6. The solid-state image pickup element according to claim 5 , wherein a depth of the at least one slit is based on a height of the at least one third OCL.

7. The solid-state image pickup element according to claim 4 , further comprising a low-reflection layer on the at least one first OCL, the at least one second OCL, and the at least one third OCL.

8. The solid-state image pickup element according to claim 4 , wherein
a size of the at least one second OCL is equal to a size of the at least one first OCL in the pixel area, and
the size of the at least one second OCL is viewed in a plan view with a direction of viewing normal to an active surface of the chip.

9. The solid-state image pickup element according to claim 4 , wherein the pixel area and the dam area are separated by at least one pixel of the plurality of pixels.

10. The solid-state image pickup element according to claim 4 , wherein
a size of the at least one third OCL is an integral multiple of a size of the at least one first OCL, and
the size of the at least one third OCL is viewed in a plan view with a direction of viewing normal to an active surface of the chip.

11. The solid-state image pickup element according to claim 1 , wherein each pixel of the plurality of pixels comprises at least one on-chip lens (OCL), a low-reflection layer, and a color filter layer.

12. The solid-state image pickup element according to claim 5 ,
wherein
the dam area comprises a slit area,
the slit area comprises the at least one slit and the at least one third OCL, and
a distance between an outer periphery of the slit area to the at least one slit is equal to or greater than a sum of a radius of the at least one first OCL and a formation position error in a plane direction when the at least one slit is formed in the at least one third OCL.

13. An electronic equipment, comprising:
a solid-state image pickup element including:
a pixel area comprising a plurality of pixels arranged two-dimensionally in a matrix;
a chip mounting area in which a chip is flip-chip mounted; and
a dam area, around the chip mounting area, in which a plurality of slits is formed,
wherein
the plurality of slits is configured to block an outflow of an underfill resin and an outflow of a light-shielding resin,
the plurality of slits comprises a first plurality of slits and a second plurality of slits,
a distance between the first plurality of slits and the pixel area is smaller than a distance between the second plurality of slits and the pixel area,
the first plurality of slits is configured to block the outflow of the light-shielding resin into the pixel area, and
the second plurality of slits is configured to block the outflow of the underfill resin into the pixel area.

14. A semiconductor apparatus, comprising:
an on-chip lens (OCL) area comprising at least one first OCL in a matrix;
a chip mounting area in which a chip is flip-chip mounted; and
a dam area, around the chip mounting area, in which a plurality of slits is formed,
wherein
the OCL area corresponds to a pixel area,
the plurality of slits is configured to block an outflow of an underfill resin and an outflow of a light-shielding resin,
the plurality of slits comprises a first plurality of slits and a second plurality of slits,
a distance between the first plurality of slits and the pixel area is smaller than a distance between the second plurality of slits and the pixel area,
the first plurality of slits is configured to block the outflow of the light-shielding resin into the pixel area, and
the second plurality of slits is configured to block the outflow of the underfill resin into the pixel area.

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Fujimagari Junichiro
• Ohkubo Tomohiro

Classifications

• H10W90/732

  between stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/387

  Flow barriers · CPC title

• H10W72/073

  of die-attach connectors · CPC title