Silicon carbide semiconductor device having a conductive layer formed above a bottom surface of a well region so as not to be in ohmic connection with the well region and power converter including the same

Patent metadata

Field	Value
Publication number	US-11646369-B2
Application number	US-202117202347-A
Country	US
Kind code	B2
Filing date	Mar 16, 2021
Priority date	Feb 24, 2017
Publication date	May 9, 2023
Grant date	May 9, 2023

Abstract

In an SiC-MOSFET with a built-in Schottky diode, a bipolar current may be passed in a second well region formed at a terminal part to reduce a breakdown voltage. In the SiC-MOSFET with the built-in Schottky diode, a conductive layer in Schottky connection with the second well region is provided on the second well region in the terminal part, and the conductive layer is electrically connected with a source electrode of the MOSFET. A conductive layer contact hole is provided for connecting only the conductive layer and the source electrode.

First claim

The invention claimed is:

1. A silicon carbide semiconductor device comprising:
a semiconductor substrate of a first conductivity type made of silicon carbide;
a drift layer of the first conductivity type formed on the semiconductor substrate;
a first well region of a second conductivity type provided in a surface layer of the drift layer;
a source region of the first conductivity type formed in a surface layer area of the first well region;
a channel epitaxial layer of the first conductivity type formed on a surface of the first well region;
an ohmic electrode provided in a first well region contact hole on the first well region and in ohmic connection with the first well region;
a gate insulating film formed on the first well region;
a second well region of the second conductivity type provided in the surface layer of the drift layer separately from the first well region;
a gate electrode formed on the gate insulating film on the first well region and on an insulating film provided on the second well region;
a gate pad formed above the second well region and connected with the gate electrode;
a conductive layer formed above the bottom surface of the second well region so as not to be in ohmic connection with the second well region, the conductive layer being lower in sheet resistance than the second well region;
a source electrode connected with the ohmic electrode and the conductive layer; and
a conductive layer contact hole forming ohmic connection between the conductive layer and the source electrode, while forming no ohmic connection between the conductive layer and the second well region.

2. The silicon carbide semiconductor device according to claim 1 , wherein
the first well region and the second well region are separated from each other.

3. The silicon carbide semiconductor device according to claim 1 , wherein
the second well region is in ohmic connection with the source electrode through a second well region contact hole, and
the conductive layer contact hole and the second well region contact hole are separated from each other by 10 μm or more on a shortest path in the second well region in a plane direction.

4. The silicon carbide semiconductor device according to claim 1 , wherein
the first well region contact hole is separated from the conductive layer contact hole by 10 μm or more on a shortest path in the first well region or the second well region in a plane direction.

5. The silicon carbide semiconductor device according to claim 1 , wherein
the conductive layer is a silicon carbide conductive layer made of silicon carbide of the first conductivity type formed in a surface layer area on the second well region.

6. The silicon carbide semiconductor device according to claim 5 , wherein
the silicon carbide conductive layer is buried in the second well region in a depth direction in a cross section.

7. The silicon carbide semiconductor device according to claim 5 , wherein
the silicon carbide conductive layer has a lower surface with recesses and projections.

8. The silicon carbide semiconductor device according to claim 1 , wherein
the conductive layer is formed on a surface of the second well region, and
the conductive layer and the second well region are in Schottky connection with each other.

9. The silicon carbide semiconductor device according to claim 8 , wherein
the conductive layer is made of polycrystalline silicon.

10. The silicon carbide semiconductor device according to claim 8 , wherein
the conductive layer is in Schottky connection with a fifth separation region of the first conductivity type penetrating the second well region.

11. The silicon carbide semiconductor device according to claim 1 , wherein
the conductive layer is formed over the second well region across an insulating layer.

12. The silicon carbide semiconductor device according to claim 1 , wherein
the conductive layer is formed to extend over a width corresponding to a half or more of the width of the second well region in a lateral direction in a cross section.

13. The silicon carbide semiconductor device according to claim 1 , comprising:
a fourth separation region of the first conductivity type provided inside the second well region in a plane direction; and
a second Schottky electrode provided on the fourth separation region and in Schottky connection with the fourth separation region, wherein
the second Schottky electrode is connected with the source electrode.

14. The silicon carbide semiconductor device according to claim 13 , wherein
the second Schottky electrode and the conductive layer are connected in a contact hole same as a contact hole for the source electrode.

15. The silicon carbide semiconductor device according to claim 1 , wherein
the conductive layer is formed below the gate pad or the gate electrode.

16. The silicon carbide semiconductor device according to claim 1 , wherein
the gate electrode is provided over a part of the second well region across the gate insulating film,
the silicon carbide semiconductor device comprising an electric field relaxing layer lower in impurity concentration than the second well region and provided at the part where the second well region faces the gate electrode across the gate insulating film.

17. A power converter comprising:
a main converter circuit including the silicon carbide semiconductor device according to claim 1 , and converting input power and outputting the converted power;
a drive circuit that outputs a drive signal for driving the silicon carbide semiconductor device to the silicon carbide semiconductor device; and
a control circuit that outputs a control signal for controlling the drive circuit to the drive circuit.

18. A silicon carbide semiconductor device comprising:
a semiconductor substrate of a first conductivity type made of silicon carbide;
a drift layer of the first conductivity type formed on the semiconductor substrate;
a first well region of a second conductivity type provided in a surface layer of the drift layer;
a source region of the first conductivity type formed in a surface layer area of the first well region;
a channel epitaxial layer of the first conductivity type formed on a surface of the first well region;
an ohmic electrode provided on the first well region and in ohmic connection with the first well region;
a gate insulating film formed on the first well region;
a second well region of the second conductivity type provided in the surface layer of the drift layer to be continuous with at least one of the first well regions;
a gate electrode formed on the gate insulating film on the first well region and on an insulating film provided on the second well region;
a gate pad formed above the second well region and connected with the gate electrode;
a conductive layer formed above the bottom surface of the second well region so as not to be in ohmic connection with the second well region, the conductive layer having an area half or more of the area of the second well region below the gate pad and being lower in sheet resistance than the second well region; and
a source electrode connected with the ohmic electrode and the conductive layer, wherein
the second well region is in ohmic connection with the source electrode through a first well region contact hole on the first well region.

19. The silicon carbide semiconductor device according to claim 18 , wherein
the conductive layer is a silicon carbide conductive layer made of silicon carbide of the first conductivity t

Assignees

• Mitsubishi Electric Corp

Inventors

• NAGAHISA Yuichi
• Hino Shiro
• Sadamatsu Koji
• Hatta Hideyuki
• Kawahara Kotaro

Classifications

• H10D64/252

  for vertical or pseudo-vertical devices · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10D8/60

  Schottky-barrier diodes · CPC title

• H10D84/143

  the built-in components being PN junction diodes · CPC title

• H10D84/0126

  the components including insulated gates, e.g. IGFETs · CPC title