Chip resistor and method of manufacturing chip resistor

US11646136B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11646136-B2
Application numberUS-202217703798-A
CountryUS
Kind codeB2
Filing dateMar 24, 2022
Priority dateApr 5, 2021
Publication dateMay 9, 2023
Grant dateMay 9, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A chip resistor includes an insulated substrate having a rectangular parallelepiped shape, a first front electrode and a second front electrode created on both longitudinal ends of the insulated substrate, and a resistive element making a connection between the first and second front electrodes. The resistive element is formed in a meandering shape with a first region and a second region continuing in series via a jointing section between a pair of connecting portions. Moreover, in the first region, a first trimming groove for rough adjustment is formed to elongate a current path of the resistive element. In the second region, a second trimming groove is formed for fine adjustment extending in a direction angled with respect to a straight line along a direction in which the first trimming groove extends.

First claim

Opening claim text (preview).

What is claimed is: 1. A chip resistor comprising: an insulated substrate having a rectangular parallelepiped shape; a pair of electrodes placed opposing each other across a certain distance on the insulated substrate; and a resistive element making a bridge connection between the pair of electrodes with a trimming groove extending linearly in the resistive element to make a resistance value adjustment, wherein the resistive element is an element formed by printing having connecting portions connecting to the pair of the electrodes and an adjustment part which is rectangular in shape positioned between both the connecting portions; in the adjustment part, a first trimming groove for rough adjustment is formed to elongate a current path of the resistive element and a second trimming groove for fine adjustment is formed to adjust a resistance value after being roughly adjusted by the first trimming groove; the first trimming groove and the second trimming groove extend from one common side or two opposing sides of the adjustment part as their respective starting point; the first trimming groove and the second trimming groove do not touch each other; and a straight line along a direction in which the second trimming grove extends is angled with respect to a straight line along a direction in which the first trimming groove extends, with an angle of inclination being greater than zero and smaller than 90°. 2. The chip resistor according to claim 1 , wherein at least one of the connecting portions is made as a turn segment extending in a meandering shape. 3. The chip resistor according to claim 1 , wherein the adjustment part has a first region and a second region continuing in series via a jointing portion, the first trimming groove is formed in the first region, and the second trimming groove is formed in the second region. 4. The chip resistor according to claim 3 , wherein, as the first trimming groove, a plurality of first trimming grooves that are I-cut shaped and have different length dimensions are formed in the first region. 5. The chip resistor according to claim 4 , wherein, as the first trimming groove, two first trimming grooves are formed in the first region and one of the first trimming grooves is angled with respect to the other one of the first trimming grooves. 6. The chip resistor according to claim 3 , wherein, as the first trimming groove, two first trimming grooves are formed in the first region and the two first trimming grooves extend in opposite directions to each other originating from top and bottom opposing sides of the first region. 7. A method of manufacturing a chip resistor including an insulated substrate, a first electrode and a second electrode placed opposing each other across a certain distance on the insulated substrate, and a resistive element making a bridge connection between the first electrode and the second electrode with a trimming groove extending linearly in the resistive element to make a resistance value adjustment, wherein the resistive element includes an element formed by printing having a turn segment connecting to the first electrode and extending in a meandering shape, a first region which is rectangular in shape and connects to the turn segment, a second region which is rectangular in shape and connects to the second electrode, and a jointing portion making a connection between the first region and the second region, and the method comprises: forming in the first region a first trimming groove for rough adjustment to elongate a current path of the resistive element; subsequently forming in the second region a second trimming groove, wherein the first trimming groove and the second trimming groove extend from one common side of the first and second regions or from two opposing sides of the first and second regions as their respective starting point, the first trimming groove and the second trimming groove do not touch each other, and a straight line along a direction in which the second trimming groove extends is angled with respect to a straight line along a direction in which the first trimming groove extends, with an angle of inclination being greater than zero and smaller than 90°; and thereby making a fine adjustment of a resistance value after being roughly adjusted by the first trimming groove so that the resistance value falls within a target resistance value range. 8. The chip resistor according to claim 2 , wherein the adjustment part has a first region and a second region continuing in series via a jointing portion, the first trimming groove is formed in the first region, and the second trimming groove is formed in the second region. 9. The chip resistor according to claim 8 , wherein, as the first trimming groove, a plurality of first trimming grooves that are I-cut shaped and have different length dimensions are formed in the first region. 10. The chip resistor according to claim 9 , wherein, as the first trimming groove, two first trimming grooves are formed in the first region and one of the first trimming grooves is angled with respect to the other one of the first trimming grooves. 11. The chip resistor according to claim 8 , wherein, as the first trimming groove, two first trimming grooves are formed in the first region and the two first trimming grooves extend in opposite directions to each other originating from top and bottom opposing sides of the first region.

Assignees

Inventors

Classifications

  • H01C7/00Primary

    Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material (consisting of loose powdered or granular material H01C8/00; resistors having potential barriers, e.g. field-effect resistors, H10D1/40 - H10D1/43, H10K10/10; semiconductor devices sensitive to electromagnetic or corpuscular radiation, e.g. photoresistors, H10F30/00; magnetic field controlled resistors H10N50/10; bulk negative resistance effect devices H10N80/00) · CPC title

  • adapted for trimming · CPC title

  • adapted for manufacturing resistor chips · CPC title

  • by removing or adding resistive material (H01C17/23, H01C17/232, H01C17/235 take precedence) · CPC title

  • H01C7/003Primary

    Thick film resistors · CPC title

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What does patent US11646136B2 cover?
A chip resistor includes an insulated substrate having a rectangular parallelepiped shape, a first front electrode and a second front electrode created on both longitudinal ends of the insulated substrate, and a resistive element making a connection between the first and second front electrodes. The resistive element is formed in a meandering shape with a first region and a second region contin…
Who is the assignee on this patent?
Koa Corp
What technology area does this patent fall under?
Primary CPC classification H01C7/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 09 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).