Phase lock loop circuit based adjustment of a measurement time window in an optical measurement system

Patent metadata

Field	Value
Publication number	US-11645483-B2
Application number	US-202117202572-A
Country	US
Kind code	B2
Filing date	Mar 16, 2021
Priority date	Mar 20, 2020
Publication date	May 9, 2023
Grant date	May 9, 2023

Abstract

An exemplary system includes a photodetector configured to generate a photodetector output pulse when the photodetector detects a photon from a light pulse having a light pulse time period, a TDC configured to monitor for the occurrence of the photodetector output pulse during a measurement time window that is within and shorter in duration than the light pulse time period, a PLL circuit for the TDC, and a precision timing circuit connected to the PLL circuit and configured to adjust, based on at least one signal generated within the PLL circuit, a temporal position of the measurement time window within the light pulse time period.

First claim

What is claimed is:

1. A system comprising:
a photodetector configured to generate a photodetector output pulse when the photodetector detects a photon from a light pulse having a light pulse time period;
a time-to-digital converter (TDC) configured to monitor for an occurrence of the photodetector output pulse during a measurement time window that is within and shorter in duration than the light pulse time period;
a phase lock loop (PLL) circuit for the TDC and having a PLL feedback period defined by a reference clock, the PLL circuit comprising:
a voltage controlled oscillator configured to lock to the reference clock and having a plurality of stages configured to output a plurality of fine phase signals each having a different phase; and
a feedback divider configured to be clocked by a single fine phase signal included in the plurality of fine phase signals and have a plurality of feedback divider states during the PLL feedback period; and

a precision timing circuit connected to the PLL circuit and configured to:
adjust, based on one or more of the fine phase signals or one or more signals representative of the feedback divider states, a temporal position of the measurement time window within the light pulse time period,
generate a timing pulse, and
set, based on a combination of one of the fine phase signals and one of the feedback divider states, a temporal position of the timing pulse within the PLL feedback period.

2. The system of claim 1 , wherein:
the light pulse is included in a sequence of light pulses generated by a light source and each having the light pulse time period;
the system further includes a measurement time window management circuit configured to
direct the precision timing circuit to sweep the measurement time window across the light pulse time period while the sequence of light pulses are being generated, the sweeping resulting in a temporal point spread function (TPSF) being generated based on timestamp symbols recorded by the TDC while the measurement time window is being swept,
determine a property of the TPSF,
identify, based on the property of the TPSF, a temporal location within the light pulse time period, and
direct the precision timing circuit to adjust the temporal position of the measurement time window to align a particular time bin within the measurement time window with the temporal location within the light pulse time period.

3. The system of claim 2 , wherein the measurement time window management circuit is configured to periodically repeat the directing of the precision timing circuit to sweep the measurement time window across the light pulse time period, the determining of the property of the TPSF, the identifying of the temporal location within the light pulse time period, and the directing of the precision timing circuit to adjust the temporal position of the measurement time window.

4. The system of claim 2 , wherein the measurement time window management circuit is configured to:
receive a command to perform a calibration of the TDC; and
perform, in response to the command to perform the calibration of the TDC, the directing of the precision timing circuit to sweep the measurement time window across the light pulse time period, the determining of the property of the TPSF, the identifying of the temporal location within the light pulse time period, and the directing of the precision timing circuit to adjust the temporal position of the measurement time window.

5. The system of claim 2 , wherein:
the property of the TPSF comprises a peak value of the TPSF; and
the temporal location within the light pulse time period corresponds to a temporal position of the peak value.

6. The system of claim 2 , wherein the property of the TPSF comprises one or more of a full width at half maximum metric associated with the TPSF, a center of mass associated with the TPSF, a fitting metric associated with the TPSF, or a cross-correlation metric associated with the TPSF.

7. The system of claim 1 , wherein:
the feedback divider is configured to generate a load signal; and
the precision timing circuit comprises:
a phase intersection block configured to generate, based on the fine phase signals and the feedback divider states, an output signal with a programmable phase, and
circuitry configured to selectively provide either the load signal or the output signal to a phase detector included in the PLL circuit;

wherein the precision timing circuit is configured to adjust the temporal position of the measurement time window by providing the output signal to the phase detector.

8. The system of claim 7 , wherein the precision timing circuit further comprises:
a quadrature clock block configured to select, from the plurality of fine phase signals, four fine phase signals that are quadrature shifted from each other for use as quadrature clock signals; and
the phase intersection block is configured to:
receive the plurality of fine phase signals;
receive the quadrature clock signals;
receive a programmable target state signal identifying a target feedback divider state included in the plurality of feedback divider states;
receive a programmable target fine phase signal identifying a target fine phase signal included in the plurality of fine phase signals and that, in combination with the target feedback divider state, sets a desired phase of a pulse in the output signal;
generate a combination match signal when a current feedback divider state matches the target feedback state;
use the quadrature clock signals to generate four registered match signals representative of the combination match signal, the four registered match signals quadrature shifted from each other;
select a particular match signal from the four registered match signal that is aligned with a pulse included in the target fine phase signal; and
input the selected match signal and the target fine phase signal into an AND gate to output the pulse of the output signal at a temporal position that corresponds to the desired phase.

9. The system of claim 1 , further comprising a timestamp generation circuit configured to:
generate, based on a subset of the fine phase signals that define a plurality of fine states for the plurality of fine phase signals, a timestamp signal bus representative of a plurality of timestamp symbols that define the measurement time window; and
transmit the timestamp signal bus to the TDC.

10. The system of claim 1 , wherein:
the TDC is included in a plurality of TDCs;
the PLL circuit is for all of the plurality of TDCs; and
the measurement time window is for all of the plurality of TDCs.

11. The system of claim 1 , wherein the photodetector comprises a single photon avalanche diode (SPAD).

12. The system of claim 1 , wherein the photodetector is included in a wearable device configured to be worn by a user.

13. The system of claim 12 , wherein the wearable device includes a head-mountable component configured to be worn on a head of the user.

14. A wearable system for use by a user, comprising:
a head-mountable component configured to be attached to a head of the user, the head-mountable component comprising a photodetector configured to generate a photodetector output pulse when the photodetector detects a photon from a light pulse having a light pulse time period;
a time-to-digital converter (TDC) configured to monitor for an occurrence of the photodetector output pulse during a measurement time window that is within and shorter in duration than the light pulse time period;
a phase lock loop (PLL) circuit for the TDC and having a PLL feedback period defined by a refe

Assignees

• Hi Llc

Inventors

• Field Ryan
• Dahle Jacob
• Jin Rong
• Do Valle Bruno
• Sorgenfrei Sebastian

Classifications

• G06K7/10732 Primary

  Light sources · CPC title

• A61B2562/046

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• G02B27/0172

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• G06F3/015

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• A61B5/4064

  Evaluating the brain (for intracranial pressure A61B5/031; for cerebral blood gases A61B5/14553; using EEG A61B5/369) · CPC title