Distributed memory-augmented neural network architecture

Patent metadata

Field	Value
Publication number	US-11645206-B2
Application number	US-202117472764-A
Country	US
Kind code	B2
Filing date	Sep 13, 2021
Priority date	Apr 2, 2020
Publication date	May 9, 2023
Grant date	May 9, 2023

Abstract

A method for using a distributed memory device in a memory augmented neural network system includes receiving, by a controller, an input query to access data stored in the distributed memory device, the distributed memory device comprising a plurality of memory banks. The method further includes determining, by the controller, a memory bank selector that identifies a memory bank from the distributed memory device for memory access, wherein the memory bank selector is determined based on a type of workload associated with the input query. The method further includes computing, by the controller and by using content based access, a memory address in the identified memory bank. The method further includes generating, by the controller, an output in response to the input query by accessing the memory address.

First claim

What is claimed is:

1. A computer-implemented method, comprising:
receiving, by a controller neural network, an input;
generating, by the controller neural network, parameters including (i) a key vector and (ii) a selector vector to interface with a plurality of memory banks that are in communication with the controller neural network via a memory subsystem;
selecting, by the memory subsystem, at least one of the memory banks for the controller neural network to access, using the selector vector and the key vector; and
accessing, by the controller neural network, a memory address from the selected memory bank using the key vector.

2. The computer-implemented method of claim 1 , wherein one or more of the memory banks, the subsystem, and the controller neural network comprise field programmable gate array (FPGA) devices.

3. The computer-implemented method of claim 1 , wherein the accessing the memory address from the selected memory bank comprises:
generating a memory query vector by reading data from the selected memory bank;
determining a similarity metric between the input with the memory query vector; and
determining the memory address based on the similarity metric.

4. The computer-implemented method of claim 1 , wherein the selector vector is generated based on training and/or the input.

5. The computer-implemented method of claim 1 , wherein the selector vector produces at least one of the following: preferred biases, circuit timings, stability and/or write assist parameters for the memory banks.

6. The computer-implemented method of claim 1 , wherein the memory banks are in a distributed memory device and are heterogeneous, with a first memory bank in the distributed memory device having attributes that are distinct from those of a second memory bank in the distributed memory device.

7. The computer-implemented method of claim 1 , wherein the memory banks are in a distributed memory device and are homogenous, with the memory banks having substantially same attributes.

8. A neural network system, comprising:
a distributed memory device comprising a plurality of memory banks; and
a controller coupled with the distributed memory device, to access data stored in the distributed memory device, the controller configured to:
in response to an input, generate parameters including (i) a key vector and (ii) a selector vector to interface with the plurality of memory banks;
select, at least one of the memory banks for the controller neural network to access, using the selector vector and the key vector; and
access a memory address from the selected memory bank using the key vector.

9. The system of claim 8 , wherein one or more of the memory banks, the distributed memory device, and the controller neural network comprise field programmable gate array (FPGA) devices.

10. The system of claim 8 , wherein the accessing the memory address from the selected memory bank comprises:
generating a memory query vector by reading data from the selected memory bank;
determining a similarity metric between the input with the memory query vector; and
determining the memory address based on the similarity metric.

11. The system of claim 8 , wherein the selector vector is generated based on training and/or the input.

12. The system of claim 8 , wherein the selector vector produces at least one of the following: preferred biases, circuit timings, stability and/or write assist parameters for the memory banks.

13. The system of claim 8 , wherein the memory banks are in a distributed memory device and are heterogeneous, with a first memory bank in the distributed memory device having attributes that are distinct from those of a second memory bank in the distributed memory device.

14. The system of claim 8 , wherein the memory banks are in a distributed memory device and are homogenous, with the memory banks having substantially same attributes.

15. A memory address determination apparatus, comprising:
a controller configured to access data stored in a distributed memory device, the controller further configured to:
in response to an input, generate parameters including (i) a key vector and (ii) a selector vector to interface with the plurality of memory banks;
select, at least one of the memory banks for the controller neural network to access, using the selector vector and the key vector; and
access a memory address from the selected memory bank using the key vector.

16. The memory address determination apparatus of claim 15 , wherein the accessing the memory address from the selected memory bank comprises:
generating a memory query vector by reading data from the selected memory bank;
determining a similarity metric between the input with the memory query vector; and
determining the memory address based on the similarity metric.

17. The memory address determination apparatus of claim 15 , wherein the selector vector is generated based on training and/or the input.

18. The memory address determination apparatus of claim 15 , wherein the selector vector produces at least one of the following: preferred biases, circuit timings, stability and/or write assist parameters for the memory banks.

19. The memory address determination apparatus of claim 15 , wherein the memory banks are in a distributed memory device and are heterogeneous, with a first memory bank in the distributed memory device having attributes that are distinct from those of a second memory bank in the distributed memory device.

20. The memory address determination apparatus of claim 15 , wherein the memory banks are in a distributed memory device and are homogenous, with the memory banks having substantially same attributes.

Assignees

• IBM

Inventors

• Ozcan Ahmet Serkan
• Kornuta Tomasz
• Radens Carl
• Antoine Nicolas

Classifications

• G06N3/0442

  characterised by memory or gating, e.g. long short-term memory [LSTM] or gated recurrent units [GRU] · CPC title

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G06F12/0824 Primary

  Distributed directories, e.g. linked lists of caches · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C11/54

  using elements simulating biological cells, e.g. neuron · CPC title