Storage controller, computational storage device, and operational method of computational storage device

Patent metadata

Field	Value
Publication number	US-11645011-B2
Application number	US-202217829980-A
Country	US
Kind code	B2
Filing date	Jun 1, 2022
Priority date	Jun 17, 2021
Publication date	May 9, 2023
Grant date	May 9, 2023

Abstract

A computational storage device includes a non-volatile memory (NVM) device; and a storage controller configured to control the NVM device. The storage controller includes: a computation processor configured to execute an internal application to generate an internal command; a host interface circuit configured to receive a host command from an external host device, to receive the internal command from the computation processor, and to individually process the received host command and the received internal command; a flash translation layer (FTL) configured to perform an address mapping operation based on a result of the processing of the host interface circuit; and a memory interface circuit configured to control the NVM device based on the address mapping operation of the FTL.

First claim

What is claimed is:

1. A computational storage device comprising:
a non-volatile memory (NVM) device; and
a storage controller configured to control the NVM device,
wherein the storage controller includes:
a computation processor configured to execute an internal application to generate an internal command;
a host interface circuit configured to communicate with the computation processor through an NVM express (NVMe) interface virtualized on a system bus, to receive a host command from an external host device, to receive the internal command from the computation processor via the NVMe interface, and to individually process the received host command and the received internal command;
a flash translation layer (FTL) configured to perform a first address mapping operation based on a result of the processing by the host interface circuit of the received host command, and to perform a second address mapping operation based on a result of the processing by the host interface circuit of the received internal command; and
a memory interface circuit configured to control the NVM device based on the first address mapping operation and the section address mapping operation of the FTL.

2. The computational storage device of claim 1 ,
wherein the computation processor, the host interface circuit, the FTL, and the memory interface circuit communicate with each other through the system bus.

3. The computational storage device of claim 2 , wherein the host interface circuit is configured to communicate with the external host device through a first interface.

4. The computational storage device of claim 3 , wherein the first interface is an NVM express (NVMe) interface.

5. The computational storage device of claim 2 , wherein the host interface circuit includes:
a physical port configured to transmit and receive a physical signal to and from the external host device, respectively; and
an NVMe processor configured to receive the host command through the physical port and to receive the internal command through the system bus.

6. The computational storage device of claim 5 , wherein the NVM device is divided into a first namespace and a second namespace, and
wherein the NVMe processor is further configured to process the host command with respect to the first namespace and to process the internal command with respect to the second namespace.

7. The computational storage device of claim 2 , wherein the host interface circuit includes:
a physical port configured to transmit and receive a physical signal to and from the external host device, respectively;
a first NVMe processor configured to receive the host command through the physical port; and
a second NVMe processor configured to receive the internal command through the system bus.

8. The computational storage device of claim 7 , wherein the NVM device is divided into a first namespace, a second namespace, and a third namespace,
wherein the first NVMe processor is further configured to process the host command with respect to the first namespace,
wherein the second NVMe processor is further configured to process the internal command with respect to the second namespace, and
wherein the first NVMe processor and the second NVMe processor share the third namespace.

9. The computational storage device of claim 1 , wherein the storage controller further includes a controller memory,
wherein the controller memory includes an internal submission queue and an internal completion queue that correspond to the internal command.

10. The computational storage device of claim 9 , wherein the computation processor is further configured to add the internal command to the internal submission queue of the controller memory through the host interface circuit, and
wherein the host interface circuit receives the internal command from the internal submission queue of the controller memory.

11. The computational storage device of claim 9 , wherein the computation processor is further configured to directly add the internal command to the internal submission queue of the controller memory, and
wherein the host interface circuit is further configured to receive doorbell signaling from the computation processor and receive the internal command by fetching the internal command from the internal submission queue of the controller memory in response to the doorbell signaling.

12. The computational storage device of claim 1 , wherein the host interface circuit is further configured to:
receive doorbell signaling from the external host device; and
receive the host command by fetching the host command from a host submission queue of a host memory of the external host device in response to the doorbell signaling.

13. The computational storage device of claim 1 , wherein the FTL includes:
an FTL accelerator configured to perform the first address mapping operation and the second address mapping operation;
a read buffer circuit configured to manage read data received through the memory interface circuit; and
a write buffer circuit configured to manage write data received through the host interface circuit, and
wherein the FTL accelerator, the read buffer circuit, and the write buffer circuit are hardware circuits.

14. An operational method of a computational storage device, the operational method comprising:
receiving, by a physical port, a host command from an external host device;
processing the host command through a non-volatile memory express (NVMe) processor;
performing, by a flash translation layer (FTL), first address mapping for the processed host command;
accessing, by a memory interface circuit, an NVM device based on the first address mapping;
generating, by a computation processor executing an internal application, an internal command;
processing the internal command through the NVMe processor;
performing, by the FTL, second address mapping for the processed internal command; and
accessing, by the memory interface circuit, the NVM device based on the second address mapping.

15. The operational method of claim 14 , wherein the generating the internal command by the computation processor further includes:
receiving, by the physical port, an execute command from the external host device;
transferring, by the physical port, the execute command to the computation processor; and
executing, by the computation processor, the internal application in response to the execute command and generating the internal command based on the executing the internal application.

16. The operational method of claim 14 , wherein the generating the internal command by the computation processor further includes:
receiving, by the physical port, an execute command from the external host device;
receiving, by the NVMe processor, the execute command from the physical port;
transferring, by the NVMe processor, the execute command to the computation processor; and
executing, by the computation processor, the internal application in response to the execute command and generating the internal command depending on the executing the internal application.

17. The operational method of claim 14 , wherein the internal application is stored in a controller memory of the computational storage device.

18. A storage controller configured to control a non-volatile memory (NVM) device comprising:
an NVM express (NVMe) processor configured to receive a host command through an external host driver;
a flash translation layer (FTL) configured to perform address mapping under control of the NVMe processor;
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Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Hwang
• Heo Wan

Classifications

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F3/0679 Primary

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title