Memory system and operating method thereof for controlling a multi-plane read operation

Patent metadata

Field	Value
Publication number	US-11645008-B2
Application number	US-202117149353-A
Country	US
Kind code	B2
Filing date	Jan 14, 2021
Priority date	Jun 9, 2020
Publication date	May 9, 2023
Grant date	May 9, 2023

Abstract

An operating method of a memory system that includes a memory device including a plurality of planes and a plurality of page buffers for the plurality of planes, respectively, and a controller suitable for controlling the memory device, the operating method includes: providing, by the controller, the memory device with page read commands for respective target planes among the plurality of planes; simultaneously reading, by the memory device, data from the target planes and buffering the data in target page buffers corresponding to the respective target planes in response to the page read commands; selectively providing, by the controller, the memory device with an all-plane data output command or respective-plane data output commands from which target page addresses are omitted; and sequentially outputting, by the memory device, the data buffered in the target page buffers, in response to the all-plane data output command or the respective-plane data output commands.

First claim

What is claimed is:

1. An operating method of a memory system that includes a memory device including a plurality of planes and a plurality of page buffers for the plurality of planes, respectively, and a controller configured for controlling the memory device, the operating method comprising:
providing, by the controller, the memory device with page read commands including target page addresses of respective target planes among the plurality of planes;
simultaneously reading, by the memory device, data from the respective target planes and buffering the data in target page buffers corresponding to the respective target planes in response to the page read commands;
selectively providing, by the controller, the memory device for a sequential read operation with an all-plane data output command from which the target page addresses are omitted or for a random read operation with respective-plane data output commands from which the target page addresses are omitted; and
sequentially outputting, by the memory device without directly accessing a target page, the data buffered in the target page buffers, in response to the all-plane data output command in one clock cycle or the respective-plane data output commands in one clock cycle for each respective target plane,
wherein the all-plane data output command includes simultaneously performing, on all planes, a cache read operation in which the memory device outputs data read from a specific page through an input/output pad and simultaneously reads data from memory cells of a next page, and
wherein each respective-plane data output command corresponds one to one with each respective target plane.

2. The operating method of claim 1 , wherein the selectively providing includes providing the memory device with the all-plane data output command when all the plurality of planes are the respective target planes.

3. The operating method of claim 2 , wherein the providing the memory device with the all-plane data output command includes providing the all-plane data output command for a single command cycle.

4. The operating method of claim 1 , wherein the selectively providing includes providing the memory device with the respective-plane data output commands corresponding to the respective target planes when some of the plurality of planes are the respective target planes.

5. The operating method of claim 4 , wherein the providing the memory device with the respective-plane data output commands corresponding to the target planes includes providing each of the respective-plane data output commands for a single command cycle.

6. The operating method of claim 4 , wherein the sequentially outputting of the data buffered in the target page buffers includes:
outputting data corresponding to a page buffer corresponding to a single plane, in response to one of the respective-plane data output commands for the single plane, until all data buffered in the target page buffers are output.

7. A memory system comprising:
a memory device including a plurality of planes and a plurality of page buffers for the plurality of planes, respectively; and
a controller configured for controlling the memory device,
wherein the controller provides the memory device with page read commands including target page addresses of respective target planes among the plurality of planes,
wherein the memory device simultaneously reads data from the respective target planes and buffers the data in target page buffers corresponding to the respective target planes in response to the page read commands,
wherein the controller selectively provides the memory device for a sequential read operation with an all-plane data output command from which the target page addresses are omitted or for a random read operation with respective-plane data output commands from which the target page addresses are omitted; and
wherein the memory device sequentially outputs the data buffered in the target page buffers without directly accessing a target page, in response to the all-plane data output command in one clock cycle or the respective-plane data output commands in one clock cycle for each respective target plane,
wherein the all-plane data output command includes simultaneously performing, on all planes, a cache read operation in which the memory device outputs data read from a specific page through an input/output pad and simultaneously reads data from memory cells of a next page, and
wherein each respective-plane data output command corresponds one to one with each respective target plane.

8. The memory system of claim 7 , wherein the controller provides the memory device with the all-plane data output command when all the plurality of planes are the respective target planes.

9. The memory system of claim 8 , wherein the controller provides the all-plane data output command for a single command cycle.

10. The memory system of claim 7 , wherein the controller provides the memory device with the respective-plane data output commands corresponding to the respective target planes when some of the plurality of planes are the respective target planes.

11. The memory system of claim 10 , wherein the controller provides each of the respective-plane data output commands for a single command cycle.

12. The memory system of claim 10 , wherein the memory device sequentially outputs the data buffered in the target page buffers by repeatedly performing an operation of outputting data corresponding to a page buffer corresponding to a single plane, in response to one of the respective-plane data output commands for the single plane until all the data buffered in the target page buffers are outputted.

13. A memory system comprising:
a memory device including a plurality of planes and a plurality of page buffers corresponding to the plurality of planes; and
a controller configured to control the memory device,
wherein the controller provides the memory device with multiple read commands for the plurality of planes,
wherein the memory device simultaneously reads data from target pages of the plurality of planes and buffers the data in the plurality of page buffers in response to the multiple read commands,
wherein the controller provides the memory device with a data output command associated with all or each of the plurality of planes, the data output command configured to exclude addresses of the target pages; and
wherein the memory device sequentially outputs to the controller without directly accessing a target page, the data buffered in the plurality of page buffers, in response to the data output command associated with all of the plurality of planes in one clock cycle, and in response to the data output command associated with each of the plurality of planes in one clock cycle for each respective plane,
wherein the data output command associated with all of the plurality of planes includes simultaneously performing, on all planes, a cache read operation in which the memory device outputs data read from a specific page through an input/output pad and simultaneously reads data from memory cells of a next page, and
wherein each data output command associated with each of the plurality of planes corresponds one to one with each respective plane.

Assignees

• Sk Hynix Inc

Inventors

• Rho Jun Rye

Classifications

• G06F3/0679 Primary

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0656

  Data buffering arrangements · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0611 Primary

  in relation to response time · CPC title