Interference detection in radar receiver monitoring systems

Patent metadata

Field	Value
Publication number	US-11644530-B2
Application number	US-202017061840-A
Country	US
Kind code	B2
Filing date	Oct 2, 2020
Priority date	Oct 2, 2020
Publication date	May 9, 2023
Grant date	May 9, 2023

Abstract

A radio frequency (RF) circuit includes an input terminal configured to receive a reception signal from an antenna; an output terminal configured to output a digital output signal; a receive path including a mixer and an analog-to-digital converter (ADC), wherein the receive path is coupled to and between the input and output terminals, wherein the receive path includes an analog portion and a digital portion, and wherein the ADC generates a digital signal based on an analog signal received from the analog portion; a test signal generator configured to generate an analog test signal injected into the analog portion of the receive path; and a digital processor configured to receive a digital test signal from the digital portion, the digital test signal being derived from the analog test signal, analyze a frequency spectrum of the digital test signal, and determine a quality of the digital test signal.

First claim

What is claimed is:

1. A radio frequency (RF) circuit, comprising:
an input terminal configured to receive a reception signal from an antenna;
an output terminal configured to output a digital output signal;
a receive path comprising a mixer and an analog-to-digital converter (ADC), wherein the receive path is coupled to and between the input terminal and the output terminal, wherein the receive path includes an analog portion and a digital portion, and wherein the ADC generates a digital signal based on an analog signal received from the analog portion;
a test signal generator configured to generate an analog test signal that is injected into the analog portion of the receive path; and
a digital processor configured to:
receive a digital test signal from the digital portion of the receive path, the digital test signal being derived from the analog test signal, analyze a frequency spectrum of the digital test signal, and determine a quality of the digital test signal;
determine whether the quality of the digital test signal satisfies a predetermined criteria; and
generate, based on a first condition that the quality of the digital test signal does not satisfy the predetermined criteria, a trigger signal to retrigger the analog test signal.

2. The RF circuit of claim 1 , wherein the frequency spectrum is a Discrete Fourier transform (DFT) spectrum.

3. The RF circuit of claim 1 , wherein the digital processor is configured to determine that the quality of the digital test signal does not satisfy the predetermined criteria when a signal-to-noise ratio (SNR) of the digital test signal is less than a predetermined threshold.

4. The RF circuit of claim 1 , wherein the digital processor analyzes the frequency spectrum of the digital test signal by measuring a signal-to-noise ratio (SNR) of the digital test signal and comparing the measured SNR to a predetermined threshold, and
wherein the digital processor is configured to determine that the quality of the digital test signal does not satisfy the predetermined criteria when the SNR is less than the predetermined threshold.

5. The RF circuit of claim 1 , wherein:
the digital processor analyzes the frequency spectrum of the digital test signal by measuring a signal-to-noise ratio (SNR) of the digital test signal, calculating a SNR difference between a reference SNR and the measured SNR, and comparing the SNR difference to a predetermined threshold, and
the digital processor is configured to determine that the quality of the digital test signal does not satisfy the predetermined criteria when the SNR difference exceeds the predetermined threshold.

6. The RF circuit of claim 1 , further comprising:
a monitoring controller configured to receive the trigger signal from the digital processor, and perform a test operation in response to the trigger signal,
wherein, to perform the test operation, the monitoring controller is configured to transmit a first control signal to the test signal generator to retrigger the analog test signal.

7. The RF circuit of claim 6 , further comprising:
a transmitter configured to transmit a frequency-modulated continuous-wave (FMCW) signal during a radar operation,
wherein, to perform the test operation, the monitoring controller is configured to transmit a second control signal to the transmitter to disable the transmitter from transmitting the FMCW signal during the test operation.

8. The RF circuit of claim 1 , further comprising:
a monitoring controller configured to receive the trigger signal from the digital processor, increment a counter value of a counter in response to receiving the trigger signal, and compare the incremented counter value to a counter threshold value that has a value greater than 1,
wherein on a condition that the incremented counter value is less than the counter threshold value, the monitoring controller is configured to perform a test operation in response to the trigger signal, wherein, to perform the test operation, the monitoring controller is configured to transmit a first control signal to the test signal generator to retrigger the analog test signal, and
wherein on a condition that the incremented counter value is equal to or greater than the counter threshold value, the monitoring controller is configured to generate a fault signal.

9. The RF circuit of claim 1 , further comprising:
a monitoring controller configured to receive the trigger signal from the digital processor, increment a counter value of a counter in response to receiving the trigger signal, and compare the incremented counter value to a counter threshold value that has a value greater than 1,
wherein, on a condition that the incremented counter value is less than the counter threshold value, the monitoring controller is configured to repeat a first test operation in response to the trigger signal, wherein, to repeat the first test operation, the monitoring controller is configured to transmit a first control signal to the test signal generator to retrigger the analog test signal,
wherein, on a condition that the incremented counter value is equal to or greater than the counter threshold value, the monitoring controller is configured to transmit a second control signal to the test signal generator to initialize a second test operation,
wherein the second control signal includes reconfiguration information that modifies at least one of a frequency or a power of the analog test signal, and
wherein the test signal generator is configured to generate, during the second test operation, the analog test signal having at least one of the modified frequency or the modified power.

10. The RF circuit of claim 1 , further comprising:
a local oscillator configured to generate a reference signal; and
a directional coupler configured to couple the analog test signal into the analog portion of the receive path,
wherein the test signal generator is configured to receive the reference signal and generate the analog test signal that comprises at least one constant frequency each being offset from the reference signal, and
wherein the mixer is configured to receive the analog test signal coupled into the receive path and the reference signal from the local oscillator, and generate a mixer output signal having a test frequency comprising at least one frequency offset,
wherein the digital test signal is derived from the mixer output signal.

11. The RF circuit of claim 10 , wherein the local oscillator is configurable in a radar operation mode, during which the reference signal is a frequency-modulated continuous-wave (FMCW) signal, and a test operation mode, during which the reference signal is a continuous-wave signal having the at least one constant frequency, and
wherein the test signal generator is configured to generate the analog test signal during test operation mode.

12. The RF circuit of claim 1 , wherein on a second condition that the quality of the digital test signal satisfies the predetermined criteria, the digital processor determines that test data extracted from the digital test signal is reliable.

13. The RF circuit of claim 12 , wherein on the second condition, the digital processor is configured to analyze the digital test signal and to determine whether the receive path is in a functional safe operating mode or in a functional unsafe operating mode.

14. The RF circuit of claim 13 , wherein, in response to determining that the receive path is in the functional unsafe operating mode, the digital processor is configured to generate a fault signal and transmit the fault signal to an external device.

15. The RF ci

Assignees

• Infineon Technologies Ag

Inventors

• Melzer Alexander
• Lombardo Francesco

Classifications

• G01S13/34

  using transmission of continuous, frequency-modulated waves while heterodyning the received signal, or a signal derived therefrom, with a locally-generated signal related to the contemporaneously transmitted signal · CPC title

• G01S7/4056

  specially adapted to FMCW · CPC title

• G01S7/4069 Primary

  involving a RF signal injection · CPC title

• G01S7/023 Primary

  Interference mitigation, e.g. reducing or avoiding non-intentional interference with other HF-transmitters, base station transmitters for mobile communication or other radar systems, e.g. using electro-magnetic interference [EMI] reduction techniques (auxiliary means for detecting or identifying radar signals or the like G01S7/021; means for anti-jamming G01S7/36) · CPC title

• G01S7/028

  Miniaturisation, e.g. surface mounted device [SMD] packaging or housings · CPC title