Protection of integrated circuits

Patent metadata

Field	Value
Publication number	US-11640946-B2
Application number	US-202117466941-A
Country	US
Kind code	B2
Filing date	Sep 3, 2021
Priority date	May 18, 2018
Publication date	May 2, 2023
Grant date	May 2, 2023

Abstract

A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.

First claim

The invention claimed is:

1. An assembly, comprising:
a substrate;
substrate contacts on the substrate;
a first integrated circuit chip having a front side and a back side, and including a first plurality of electrical contacts present at the front side of the first integrated circuit chip, wherein the back side of the first integrated circuit chip includes a first plurality of trenches and does not include any electrical contacts;
a second integrated circuit chip having a front side and a back side, and including a second plurality of electrical contacts present at the front side of the second integrated circuit chip, wherein the back side of the second integrated circuit chip includes a second plurality of trenches and does not include any electrical contacts;
wherein the first and second integrated circuit chips are assembled together with their back sides facing towards each other;
wherein the first plurality of trenches are vertically aligned with the second plurality of trenches;
wherein the front side of the first integrated circuit chip is mounted to the substrate;
solder connections between the first plurality of electrical contacts present on the front side of the first integrated circuit chip and substrate contacts of the substrate; and
conductive wires electrically connecting the second plurality of electrical contacts present on the front side of the second integrated circuit chip to the substrate contacts.

2. The assembly of claim 1 , wherein front sides of the first and second integrated circuit chips each include electronic functions.

3. The assembly of claim 1 , further comprising an adhesive layer for attaching the back sides of the first and second integrated circuit chips to each other.

4. The assembly of claim 3 , wherein the adhesive layer is a glass paste.

5. The assembly of claim 1 , further comprising an adhesive film for attaching the back sides of the first and second integrated circuit chips to each other.

6. The assembly of claim 1 , wherein the back sides of the first and second integrated circuit chips each include a metal layer and the metal layers are soldered to each other.

7. The assembly of claim 1 , further comprising a molecular bond between the back side of the first integrated circuit chip and the back side of the second integrated circuit chip.

8. The assembly of claim 1 , wherein each of the first and second integrated circuit chips has an outer peripheral edge and wherein said first and second plurality of trenches are positioned offset from said outer peripheral edge.

Assignees

• St Microelectronics Grenoble 2
• St Microelectronics Rousset

Inventors

• Farison Denis
• Coffy Romain
• Riviere Jean-Michel

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W72/5473

  multiple bond wires connected to a common bond pad · CPC title

• H10W90/00 Primary

  Package configurations · CPC title