Display device and method of driving the same

Patent metadata

Field	Value
Publication number	US-11640794-B2
Application number	US-202217680612-A
Country	US
Kind code	B2
Filing date	Feb 25, 2022
Priority date	Feb 6, 2020
Publication date	May 2, 2023
Grant date	May 2, 2023

Abstract

A display device includes a first transistor including a first electrode connected to a first power line, a second electrode connected to a third node, and a gate electrode connected to a first node, a first capacitor formed between the first power line and a second node, a second capacitor formed between the first node and the second node, an emission transistor including a first electrode connected to the third node, a second electrode, and a gate electrode connected to an emission control line, and a light emitting element connected to the second electrode of the emission transistor and a second power line.

First claim

What is claimed is:

1. A display device, comprising:
a first power line;
a second power line;
a reference power line;
an initialization power line;
a data line configured to transfer a data signal;
a first scan line configured to transfer a scan signal;
a first gate line and a second gate line, configured to sequentially transfer a gate signal;
an emission control line configured to transfer an emission control signal;
a pixel, wherein the pixel comprises:
a first transistor disposed between the first power line and a third node, a gate electrode of the first transistor being connected to a first node;
a first capacitor formed between the first power line and a second node;
a second capacitor formed between the first node and the second node;
a second transistor comprising a first electrode connected to the data line, a second electrode connected to the second node, and a gate electrode connected to the first scan line;
a third transistor comprising a first electrode connected to the first node, a second electrode connected to the third node, and a gate electrode connected to the first gate line;
a fourth transistor comprising a first electrode connected to the first node, a second electrode connected to the initialization power line, and a gate electrode connected to the second gate line;
a fifth transistor comprising a first electrode connected to the second node, a second electrode connected to the reference power line, and a gate electrode connected to the first gate line;
a sixth transistor comprising a first electrode connected to the third node, a second electrode, and a gate electrode connected to the emission control line; and
a light emitting element connected between the second electrode of the sixth transistor and the second power line; and

a scan driver configured to provide the gate signal having a gate-on voltage level to the first and second gate lines and provide the scan signal having the gate-on voltage level to the first scan line,
wherein, in one frame, the scan driver alternately provides the gate signal to the first gate line and the second gate line at least twice,
wherein the scan driver provides the gate signal having the gate-on voltage level to the second gate line in a first period and a third period, provides the gate signal having the gate-on voltage level to the first gate line in a second period and a fourth period, and provides the scan signal having the gate-on voltage level to the first scan line in a scan period,
wherein the first period, the second period, the third period, and the fourth period are sequentially located in the one frame, and
wherein the first period, the second period, the third period, the fourth period, and the scan period do not overlap one another.

2. The display device of claim 1 , wherein at least one among the second transistor, the third transistor, the fourth transistor, and the fifth transistor is implemented as a dual gate transistor comprising a plurality of sub-transistors connected in series.

3. The display device of claim 1 , wherein the one frame comprises a non-emission period in which the pixel emits no light and an emission period in which the pixel emits light,
wherein the first period, the second period, the third period, the fourth period, and the scan period are included in the non-emission period,
wherein the scan driver provides the emission control signal having the gate-on voltage level to the emission control line in the emission period.

4. The display device of claim 3 , wherein a width of each of the first to fourth periods is three or more times a width of the scan period.

5. The display device of claim 4 , wherein the width of each of the first to fourth periods is four times the width of the scan period.

6. The display device of claim 4 , wherein the width of the scan period is one horizontal time interval.

7. The display device of claim 6 , wherein, in the second period, a voltage level of the first node has a voltage corresponding to a difference between a first power voltage applied to the first power line and a threshold voltage of the first transistor, wherein the voltage level of the first node is changed depending on a previous data voltage of a previous frame,
wherein, in the fourth period, the voltage level of the first node has a voltage level substantially equal to the difference between the first power voltage and the threshold voltage of the first transistor.

8. The display device of claim 6 , wherein an operation point of the first transistor in the scan period is substantially equal to the operation point of the first transistor in the emission period.

9. The display device of claim 3 , wherein the scan signal provided to a second scan line has a waveform in which the scan signal provided to the first scan line is shifted by the scan period.

10. The display device of claim 3 , wherein, between the fourth period and the scan period, the scan driver further sequentially provides the gate signal having the gate-on voltage level to the second gate line and the first gate line.

11. The display device of claim 1 , wherein the gate signal provided to the second gate line has a waveform in which the gate signal provided to the first gate line is shifted by the first period.

12. The display device of claim 1 , wherein the gate signal is provided to the second gate line and the first gate line, and the gate signal provided to the second gate line comprises a plurality of pulses having the gate-on voltage level.

13. The display device of claim 12 , wherein each of the pulses has a same pulse width,
wherein the gate signal provided to the second gate line has a waveform in which the gate signal provided to the first gate line is shifted by the pulse width.

14. A method of driving a display device, comprising:
primarily applying an initialization voltage to a first node during a first period,
wherein the display device comprises a first transistor comprising a first electrode connected to a first power line, a second electrode connected to a third node, and a gate electrode connected to the first node;
primarily applying a reference voltage to a second node in a state in which the second electrode of the first transistor and the gate electrode of the first transistor are connected, during a second period,
wherein the display device further comprises a first capacitor formed between the first power line and the second node, and a second capacitor formed between the first node and the second node;
secondarily applying the initialization voltage to the first node during a third period;
secondarily applying the reference voltage to the second node in a state in which the second electrode of the first transistor and the gate electrode of the first transistor are connected, during a fourth period;
applying a data voltage to the second node during a scan period; and
turning on an emission transistor during an emission period,
wherein the display device further comprises the emission transistor comprising a first electrode connected to the third node, a second electrode, and a gate electrode connected to an emission control line, and a light emitting element connected to the second electrode of the emission transistor and a second power line,
wherein the first to fourth periods are included in a non-emission period of one frame.

15. The method of claim 14 , wherein the first to fourth periods do not overlap one another.

16. The method of claim 15 , wherein a width of each of the first to fourth periods is three or more times a width of the scan period.

Assignees

• Samsung Display Co Ltd

Inventors

• Yang Jin Wook
• Kim Ji Hye
• Sohn Young Ha
• Lee Dong Gyu
• Jeon Jae Hyeon

Classifications

• G09G2310/0245

  Clearing or presetting the whole screen independently of waveforms, e.g. on power-on (G09G2310/063 takes precedence) · CPC title

• G09G2300/0439

  Pixel structures · CPC title

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title

• G09G3/3233 Primary

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G2300/0852

  being a dynamic memory with more than one capacitor · CPC title