Array substrate, and display panel and display device thereof

Patent metadata

Field	Value
Publication number	US-11640787-B2
Application number	US-202017279844-A
Country	US
Kind code	B2
Filing date	Jun 30, 2020
Priority date	Jun 30, 2020
Publication date	May 2, 2023
Grant date	May 2, 2023

Abstract

The present disclosure relates to an array substrate and a display panel and a display device thereof. The array substrate comprises: a substrate; a pixel array disposed on the substrate, comprising a plurality of sub-pixels arranged in a plurality of rows and a plurality of columns; a plurality of pairs of scan signal lines, extending in a row direction and being spaced apart from each other in a column direction; and a reset voltage source signal line and a data signal line, extending in the column direction.

First claim

What is claimed is:

1. An array substrate, comprising:
a substrate;
a pixel array disposed on the substrate, comprising a plurality of sub-pixels arranged in a plurality of rows and a plurality of columns, wherein each of the sub-pixels has a pixel circuit, and a data signal input terminal, a scan signal input terminal, a driving reset control signal input terminal, and a reset voltage terminal coupled to the pixel circuit, wherein the pixel circuit comprises a data writing circuit, a driving circuit and a driving reset circuit, the driving circuit comprises a control terminal, a first terminal and a second terminal, the data writing circuit is coupled to the data signal input terminal, the scan signal input terminal and the first terminal of the driving circuit, and is configured to provide a data signal to the first terminal of the driving circuit under a control of a scan signal, the driving circuit is configured to provide a driving current to a light-emitting device, the driving reset circuit is coupled to the driving reset control signal input terminal, the control terminal of the driving circuit, and the reset voltage terminal, and is configured to reset the control terminal of the driving circuit under a control of the driving reset control signal;
a plurality of pairs of scan signal lines, extending in a row direction and being spaced apart from each other in a column direction, wherein each of the plurality of pairs of scan signal lines comprises a first scan signal line and a second scan signal line, and wherein a m-th pair of scan signal lines corresponds to the sub-pixels in a m-th row, where m is greater than or equal to 1, and wherein the first scan signal line in the m-th pair of scan signal lines is configured to provide a first scan signal to the scan signal input terminal of the sub-pixel in a (2n−1)-th column from the sub-pixels in the m-th row, where n is an integer greater than or equal to 1, and wherein the second scan signal line in the m-th pair of scan signal lines is configured to provide a second scan signal to sub-pixel in a 2n-th column from the sub-pixels in the m-th row; and
a reset voltage source signal line and a data signal line, extending in the column direction, wherein the reset voltage source signal line and the data signal line are alternately arranged with each other in the row direction, and an interval between the data signal line and the reset voltage source signal line adjacent to each other defines a column of sub-pixels, and wherein the reset voltage source signal line is configured to provide a reset voltage to a reset voltage terminal of the sub-pixel in a column of sub-pixels adjacent to the reset voltage source signal line, and the data signal line is configured to provide a data signal to a data signal input terminal of the sub-pixel in a column of sub-pixels adjacent to the data signal line,
wherein a (n+1)-th reset voltage source signal line is adjacent to the sub-pixels in the 2n-th column and the sub-pixels in a (2n+1)-th column, and is configured to provide the reset voltage to the reset voltage terminals of the sub-pixels in the 2n-th column and the sub-pixels in the (2n+1)-th column, and
wherein a n-th data signal line is adjacent to the sub-pixels in the (2n−1)-th column and the sub-pixels in the 2n-th column, and is configured to provide the data signal to the data signal input terminals of the sub-pixels in the (2n−1)-th column and the sub-pixels in the 2n-th column.

2. The array substrate according to claim 1 , wherein the data signal line and the reset voltage source signal line are arranged in a same layer.

3. The array substrate according to claim 2 , further comprising a plurality of pairs of driving reset control signal lines, extending in the row direction and being spaced apart from each other in the column direction, wherein each of the plurality of pairs of driving reset control signal lines comprises a first driving reset control signal line and a second driving reset control signal line, and a m-th pair of driving reset control signal lines corresponds to the sub-pixels in the m-th row,
wherein the first driving reset control signal line in the m-th pair of driving reset control signal lines is configured to provide a first driving reset control signal to the driving reset control signal input terminal of the sub-pixel in the (2n−1)-th column from the sub-pixels in the m-th row, and the second driving reset control signal line in the m-th pair of driving reset control signal lines is configured to provide a second driving reset control signal to the driving reset control signal input terminal of the sub-pixel in a 2n-th column from the sub-pixels in the m-th row of sub-pixels.

4. The array substrate according to claim 3 , wherein the first scan signal line in the m-th pair of scan signal lines and the second driving reset control signal line in the m-th pair of driving reset control signal lines are the same signal line.

5. The array substrate according to claim 4 , wherein the pixel circuit further comprises a compensation circuit, which is coupled to the second terminal of the driving circuit, the control terminal of the driving circuit and the scan signal input terminal, and configured to perform threshold compensation on the driving circuit according to the scan signal.

6. The array substrate according to claim 5 , wherein the pixel circuit further comprises a storage circuit, coupled to a first voltage terminal and the control terminal of the driving circuit, and configured to store a voltage difference between the first voltage terminal and the control terminal of the driving circuit.

7. The array substrate according to claim 6 , wherein the sub-pixel further comprises a light-emitting control signal input terminal, and the pixel circuit further comprises a light-emitting control circuit,
wherein the light-emitting control circuit is coupled to the light-emitting control signal input terminal, the first voltage terminal, the driving circuit and the light-emitting device, and is configured to apply a first voltage of the first voltage terminal to the driving circuit, and to apply a driving current generated by the driving circuit to the light-emitting device.

8. The array substrate according to claim 7 , further comprising a plurality of light-emitting control signal lines, which extend in the column direction and are spaced apart from each other in the row direction,
wherein a m-th light-emitting control signal line is configured to be coupled to the light-emitting control signal input terminals of the sub-pixels in the m-th row to provide a light-emitting control signal.

9. The array substrate according to claim 8 , wherein the sub-pixel further comprises a light-emitting reset control signal input terminal, and the pixel circuit further comprises a light-emitting reset circuit, which is coupled to the light-emitting reset control signal input terminal, the reset voltage terminal and the light-emitting device, and configured to reset the light-emitting device under a control of a light-emitting reset control signal,
wherein the array substrate further comprises a plurality of pairs of light-emitting reset control signal lines, which extend in the row direction and are spaced apart from each other in the column direction, wherein each of the plurality of pairs of light-emitting reset control signal lines comprises a first light-emitting reset control signal line and a second light-emitting reset control signal line, and a m-th pair of light-emitting reset control signal lines corresponds to sub-pixels in the m-th row,
wherein the first light-emitting reset control signal line in the m-th pair of light-emitting reset control signal lines is configured to provide a fir

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Zhao Shuang
• Chen Chenyu
• Chen Wenbo
• Lu Hongting
• Ren Yanping
• Yang Jing

Classifications

• G09G3/3233 Primary

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G2310/061

  for resetting or blanking · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title