Counter unit

Patent metadata

Field	Value
Publication number	US-11640197-B2
Application number	US-202017605553-A
Country	US
Kind code	B2
Filing date	Mar 2, 2020
Priority date	May 10, 2019
Publication date	May 2, 2023
Grant date	May 2, 2023

Abstract

Provided is a counter unit capable of supporting any output apparatus of single-phase output, two-phase output, or three-phase output without waste. A counter unit ( 10 ) is provided with: a plurality of signal input terminals to which pulse signals outputted from a plurality of external output apparatuses ( 50 ) are respectively inputted; input circuits ( 21 a to 21 f ) respectively connected to the plurality of signal input terminals; a single-phase counter ( 13 ) that performs count on the basis of a single-phase pulse signal, and a multi-phase counter ( 15 ) that performs count on the basis of a multi-phase pulse signal; and a switching part ( 16 ) that switches whether the input circuits ( 21 a to 21 f ) are connected to the single-phase counter ( 13 ) or the multi-phase counter ( 15 ).

First claim

The invention claimed is:

1. A counter unit comprising:
a plurality of signal input terminals to which pulse signals output from a plurality of external output apparatuses are input;
an input circuit that is connected to each of the plurality of signal input terminals;
a single-phase counter that performs counting based on a single-phase pulse signal, and a multi-phase counter that performs counting based on multi-phase pulse signals, wherein the multi-phase counter is a three-phase counter that performs counting based on both two-phase pulse signals and three-phase pulse signals; and
a switching part that switches between whether the input circuit is connected to the single-phase counter or the multi-phase counter.

2. The counter unit according to claim 1 ,
wherein each of the single-phase counter and the multi-phase counter has a buffer that temporarily stores count results for a plurality of times, and
wherein the counter unit further comprises a communication part that outputs the count results for the plurality of times temporarily stored in the buffer corresponding to each of the single-phase counter and the multi-phase counter to a host device via a communication line in every predetermined communication period.

3. The counter unit according to claim 1 , further comprising:
a switching reception part that receives an instruction for a switching operation of the switching part via a communication line.

4. The counter unit according to claim 2 , further comprising:
a switching reception part that receives an instruction for a switching operation of the switching part via a communication line.

Assignees

• Omron Tateisi Electronics Co

Inventors

• Oba Hitoshi
• Kudo Masaya

Classifications

• H03K21/02 Primary

  Input circuits · CPC title

• G06F1/3287 Primary

  by switching off individual functional units in the computer system · CPC title

• G06F1/3215

  Monitoring of peripheral devices · CPC title

• G01R25/08

  by counting of standard pulses · CPC title