Clock recovery method, corresponding circuit and system

Patent metadata

Field	Value
Publication number	US-11637683-B2
Application number	US-202117335336-A
Country	US
Kind code	B2
Filing date	Jun 1, 2021
Priority date	Jun 4, 2020
Publication date	Apr 25, 2023
Grant date	Apr 25, 2023

Abstract

An input signal arranged in frames is received. The frames include a cyclic redundancy check (CRC) field including a number of bits having bit edges. A timing signal is generated to include adjustable duration waveforms at one of a first duration value and a second duration value. A CRC check determines the occurrence, over the duration, of a number of waveforms of the timing signal having their duration adjusted to one of the first duration value and the second duration value which corresponds to the number of bits. A check signal is produced having a pass/fail value. If pass, the duration of the waveforms in the timing signal is maintained adjusted to the one of the first duration value and the second duration value. If fail, the duration of the waveforms in the timing signal is re-adjusted to the other of the first duration value and the second duration value.

First claim

The invention claimed is:

1. A method, comprising:
receiving an input signal arranged in frames;
producing a timing signal including a plurality of waveforms, wherein each waveform of said plurality of waveforms has a duration adjustable to one of a first duration value and a second duration value;
sampling said input signal in response to the timing signal to extract signal data and check data from said frames;
calculating from said extracted signal data a calculated check data;
performing a check as to determine whether said calculated check data matches said extracted check data;
producing a check signal having one of a first value or a second value as a function of whether said check is passed or failed, respectively;
maintaining the duration of the waveforms in said timing signal adjusted to said one of said first duration value and said second duration value if said check signal has said first value; and
re-adjusting the duration of the waveforms in said timing signal to the other of said first duration value and said second duration value if said check signal has said second value.

2. The method of claim 1 , wherein:
said timing signal comprises a sawtooth signal and each waveform is a sawtooth waveform having a slope value adjustable at a first slope value for setting said first duration value and a second slope value for setting said second duration value; and
wherein maintaining the duration comprises maintaining said slope value of the sawtooth waveform at one of said first slope value and said second slope value; and
wherein re-adjusting the duration comprises re-adjusting said slope of the sawtooth waveform to the other of said first slope value and said second slope value.

3. The method of claim 1 , comprising:
producing a timing error signal indicative of a time offset of said timing signal with respect to the received input signal;
producing a strobe signal from the timing signal, wherein the strobe signal is used for sampling said received input signal; and
varying a frequency of said strobe signal as a function of said timing error signal targeting synchronizing said strobe signal with bit edges in said received input signal.

4. The method of claim 3 , further comprising:
generating a count value indicative of the number of waveforms of said timing signal occurring over a duration of said frames in said received input signal; and
dividing said timing error signal by said count value to produce a per-bit timing error signal; and
wherein varying comprises varying the frequency of said strobe signal as a function of said per-bit timing error signal.

5. The method of claim 4 , wherein generating the count value comprises to a nearest integer number.

6. The method of claim 4 , further comprising converting said per-bit timing error signal to a frequency error signal, wherein a frequency of said strobe signal is varied as a function of said frequency error signal.

7. The method of claim 6 , wherein converting comprises reducing a bit resolution of the per-bit timing error signal.

8. The method of claim 1 , further comprising declaring an error state if said check signal has said second value over a certain number of said frames.

9. The method of claim 1 , wherein said extracted check data is from a cyclical redundancy check field.

10. The method of claim 1 , wherein each frame includes at least one field including a plurality of bits, further comprising:
determining a duration between two homologous bit edges in said at least one field;
wherein said two homologous bit edges comprise two falling edges having no falling edges therebetween; and
setting said one of the first duration value and the second duration value as a function of the determined duration.

11. The method of claim 1 , wherein:
said extracted check data comprises a cyclic redundancy check sequence; and
performing the check comprises performing a cyclic redundancy check as a function of said cyclic redundancy check sequence.

12. A circuit, comprising:
receiver circuitry configured to receive an input signal arranged in frames;
timer circuitry configured to produce a timing signal including a plurality of waveforms, wherein each waveform of said plurality of waveforms has a duration adjustable to one of a first duration value and a second duration value;
a strobe circuit configured to sample said input signal in response to the timing signal to extract signal data and check data from said frames;
check circuitry configured to:
calculate check data from said extracted signal data;
perform a check to determine whether calculated check data matches said extracted check data; and
produce a check signal having one of a first value or a second value as a function of whether said check is passed or failed, respectively; and

wherein said timer circuitry is further configured to:
maintain the duration of the waveforms in said timing signal adjusted to said one of said first duration value and said second duration value if said check signal has said first value; and
re-adjust the duration of the waveforms in said timing signal to the other of said first duration value and said second duration value if said check signal has said second value.

13. The circuit of claim 12 , wherein:
said timing signal comprises a sawtooth signal and each waveform is a sawtooth waveform having a slope value adjustable at a first slope value for setting said first duration value and a second slope value for setting said second duration value; and
wherein the timer circuitry is further configured to:
maintain said slope value of the sawtooth waveform at one of said first slope value and said second slope value; and
re-adjust said slope of the sawtooth waveform to the other of said first slope value and said second slope value.

14. The circuit of claim 12 , wherein the timer circuitry is further configured to:
produce a timing error signal indicative of a time offset of said timing signal with respect to the received input signal;
produce a strobe signal from the timing signal, wherein the strobe signal is used for sampling said received input signal; and
vary a frequency of said strobe signal as a function of said timing error signal targeting synchronizing said strobe signal with bit edges in said received input signal.

15. The circuit of any of claim 14 , wherein said strobe signal is produced by:
generating a count value indicative of the number of waveforms of said timing signal occurring over a duration of said frames in said received input signal; and
dividing said timing error signal by said count value to produce a per-bit timing error signal; and
wherein varying comprises varying the frequency of said strobe signal as a function of said per-bit timing error signal.

16. The circuit of claim 15 , wherein said per-bit timing error signal is converted to a frequency error signal, and a frequency of said strobe signal is varied as a function of said frequency error signal.

17. The circuit of claim 16 , further comprising a bit resolution converting circuit configured to reduce a bit resolution of the per-bit timing error signal.

18. The circuit of claim 12 , wherein said extracted check data comprises a cyclical redundancy check field.

19. The circuit of claim 12 , wherein each frame includes at least one field including a plurality of bits, and wherein said receiver circuit is configured to:
determine a duration between two homologous bit edges in said at least one field;
wherein said two homologous bit edges in said re

Assignees

• St Microelectronics Srl

Inventors

• Burgio Carmelo
• Girardi Walter
• Lecce Sergio

Classifications

• H04L7/0331 Primary

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title

• H04L7/0016 Primary

  correction of synchronization errors · CPC title

• H04L7/048

  using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal · CPC title

• H04L7/0087

  Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection · CPC title

• H04L1/0061

  Error detection codes · CPC title