Integrated electronic circuit and method of making comprising a first transistor and a ferroelectric capacitor

Patent metadata

Field	Value
Publication number	US-11637111-B2
Application number	US-202117317943-A
Country	US
Kind code	B2
Filing date	May 12, 2021
Priority date	Aug 3, 2018
Publication date	Apr 25, 2023
Grant date	Apr 25, 2023

Abstract

The present invention relates to an integrated electronic circuit and method of making comprising a first transistor (1) and a ferroelectric capacitor (2). The ferroelectric capacitor (2) comprises a first electrode layer composed of a non-ferroelectric material, a ferroelectric interlayer having a thickness that is less than the thickness of the first electrode layer, and a second electrode layer composed of a non-ferroelectric material, wherein the ferroelectric interlayer is arranged between the first electrode layer and the second electrode layer, and the first electrode layer is electrically conductively connected to a gate terminal of the first transistor (1).

First claim

The invention claimed is:

1. An integrated electronic circuit
comprising a first transistor and
a ferroelectric capacitor comprising
a first electrode layer composed of a non-ferroelectric material,
a ferroelectric interlayer, and
a second electrode layer composed of a non-ferroelectric material, wherein the ferroelectric interlayer is arranged between the first electrode layer and the second electrode layer, and
the first electrode layer is electrically conductively connected to a gate terminal of the first transistor, wherein
a second transistor is electrically conductively connected by its drain terminal to the connection between the ferroelectric capacitor and the gate terminal of the first transistor.

2. The integrated electronic circuit according to claim 1 , wherein the thickness of the ferroelectric interlayer is less than 100 nm.

3. The integrated electronic circuit according to claim 1 , wherein the ferroelectric interlayer is made from hafnium oxide doped with silicon, aluminium, germanium, magnesium, calcium, strontium, barium, titanium, zirconium, one or a plurality of rare earth elements, or undoped hafnium oxide or from zirconium oxide doped with silicon, aluminium, germanium, magnesium, calcium, strontium, barium, titanium, one or a plurality of rare earth elements, or undoped zirconium oxide.

4. The integrated electronic circuit according to claim 1 , wherein the ferroelectric interlayer is made in multi-layered fashion and comprises at least one layer composed of an oxide layer having a thickness of less than 3 nm and a hafnium oxide layer or zirconium oxide layer having a thickness of between 3 nm and 20 nm.

5. The integrated electronic circuit according to claim 4 , wherein the oxide layer is made as an aluminium oxide layer, a silicon oxide layer or a zirconium oxide layer.

6. A method for producing an integrated electronic circuit, wherein
a first electrode layer composed of a non-ferroelectric material is applied on a surface of a semiconductor substrate,
a ferroelectric interlayer is applied on the first electrode layer, and
a second electrode layer is applied on the ferroelectric interlayer, such that the first electrode layer, the ferroelectric interlayer and the second electrode layer form a ferroelectric capacitor, wherein
the first electrode layer is electrically conductively connected to a gate terminal of a first transistor of the integrated electronic circuit, wherein a second transistor is electrically conductively connected by its drain terminal to the connection between the ferroelectric capacitor and the gate terminal of the first transistor.

7. The method according to claim 6 , wherein at least one structure made in recessed fashion relative to the surface of the semiconductor substrate is introduced into the semiconductor substrate, on which the first electrode layer, the ferroelectric interlayer and the second electrode layer are deposited on the at least one structure.

8. The method according to claim 7 , wherein the at least one structure made in recessed fashion is made as a trench, a blind hole, a pedestal-shaped structure or a rib-shaped structure.

Assignees

• Fraunhofer Ges Forschung
• Fraunhofer Ges Zur Forderung Angewandten Forschung E V

Inventors

• Seidel Konrad
• Kaempfe Thomas
• Polakowski Patrick

Classifications

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10D1/68

  Capacitors having no potential barriers · CPC title

• H01G7/06

  having a dielectric selected for the variation of its permittivity with applied voltage, i.e. ferroelectric capacitors (electrets H01G7/02) · CPC title

• H10B53/30 Primary

  characterised by the memory core region · CPC title

• H01G4/40 Primary

  Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations · CPC title