Pixel circuit, photoelectric detection substrate, photoelectric detection device and driving method

US11636800B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11636800-B2
Application numberUS-202117489612-A
CountryUS
Kind codeB2
Filing dateSep 29, 2021
Priority dateNov 27, 2020
Publication dateApr 25, 2023
Grant dateApr 25, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A pixel circuit includes: a charge storage circuit with first and second terminals thereof electrically coupled to first and second nodes, respectively; a reset circuit with first, second and third control terminals thereof electrically coupled to a reference signal line, a first initialization signal line, and a second initialization signal line, respectively, with fourth, fifth and sixth terminals thereof electrically coupled to the first node, a cathode of a photodiode and the second node, respectively; a photosensitive control circuit with first, second and third terminals thereof electrically coupled to an anode of the photodiode, the first node and the second node, respectively; an output circuit with first and second terminals thereof electrically coupled to a first level terminal and a fourth terminal of the photosensitive control circuit, respectively.

First claim

Opening claim text (preview).

What is claimed is: 1. A pixel circuit, comprising: a charge storage circuit, wherein a first terminal and a second terminal of the charge storage circuit are electrically coupled to a first node and a second node, respectively; a reset circuit, wherein a first control terminal of the reset circuit is electrically coupled to a reset control signal line, a second control terminal of the reset circuit is electrically coupled to a scan signal line; a first terminal, a second terminal and a third terminal of the reset circuit are electrically coupled to a reference signal line, a first initialization signal line, and a second initialization signal line, respectively, a fourth terminal, a fifth terminal, and a sixth terminal of the reset circuit are electrically coupled to the first node, a photodiode of the pixel circuit and the second node, respectively; a photosensitive control circuit, wherein a control terminal of the photosensitive control circuit is electrically coupled to a gate signal line; a first terminal, a second terminal and a third terminal of the photosensitive control circuit are electrically coupled to the photodiode, the first node and the second node, respectively; and an output circuit, wherein a first control terminal of the output circuit is electrically coupled to the second node, a second control terminal of the output circuit is electrically coupled to a scan signal line, a first terminal and a second terminal of the output circuit are electrically coupled to a first level terminal and a fourth terminal of the photosensitive control circuit, respectively, wherein the reset circuit includes a first reset circuit, a second reset circuit, and a third reset circuit; control terminals of the second reset circuit and the third reset circuit and a first control terminal of the first reset circuit collectively serve as the first control terminal of the reset circuit; a second control terminal of the first reset circuit serves as the second control terminal of the reset circuit; a first terminal and a second terminal of the first reset circuit serve as the first terminal and the fourth terminal of the reset circuit, respectively; a first terminal and a second terminal of the second reset circuit serve as the second terminal and the fifth terminal of the reset circuit, respectively; a first terminal and a second terminal of the third reset circuit serve as the third terminal and the sixth terminal of the reset circuit, respectively. 2. The pixel circuit according to claim 1 , wherein the photosensitive control circuit includes a first switch circuit and a second switch circuit; control terminals of the first switch circuit and the second switch circuit collectively serve as the control terminal of the photosensitive control circuit; a first terminal and a second terminal of the first switch circuit serve as the first terminal and the second terminal of the photosensitive control circuit, respectively; a first terminal and a second terminal of the second switch circuit serve as the third terminal and the fourth terminal of the photosensitive control circuit, respectively. 3. The pixel circuit according to claim 1 , wherein the output circuit includes a first driving circuit and a second driving circuit; a control terminal and a first terminal of the first driving circuit serve as the first control terminal and the first terminal of the output circuit, respectively; a second terminal of the first driving circuit and a first terminal of the second driving circuit together serve as the second terminal of the output circuit; a control terminal and a second terminal of the second driving circuit serve as the second control terminal and the third terminal of the output circuit, respectively. 4. The pixel circuit according to claim 1 , wherein the first reset circuit includes a first switch element and a second switch element; a control terminal of the first switch element and a control terminal of the second switch element serve as the first control terminal and the second control terminal of the first reset circuit, respectively; a first terminal of the first switch element and a first terminal of the second switch element together serve as the first terminal of the first reset circuit; a second terminal of the first switch element and a second terminal of the second switch element together serve as the second terminal of the first reset circuit. 5. The pixel circuit according to claim 1 , wherein the second reset circuit includes a third switch element; a control terminal, a first terminal and a second terminal of the third switch element serve as the control terminal, the first terminal and the second terminal of the second reset circuit, respectively; the third reset circuit includes a fourth switch element; a control terminal, a first terminal and a second terminal of the fourth switch element serve as the control terminal, the first terminal and the second terminal of the third reset circuit, respectively. 6. The pixel circuit according to claim 2 , wherein the first switch circuit includes a fifth switch element; a control terminal, a first terminal and a second terminal of the fifth switch element serve as the control terminal, the first terminal and the second terminal of the first switch circuit, respectively; the second switch circuit includes a sixth switch element; a control terminal, a first terminal and a second terminal of the sixth switch element serve as the control terminal, the first terminal and the second terminal of the second switch circuit, respectively. 7. The pixel circuit according to claim 3 , wherein the first driving circuit includes a seventh switch element; a control terminal, a first terminal and a second terminal of the seventh switch element serve as the control terminal, the first terminal and the second terminal of the first driving circuit, respectively; the second driving circuit includes an eighth switch element; a control terminal, a first terminal and a second terminal of the eighth switch element serve as the control terminal, the first terminal and the second terminal of the second driving circuit, respectively. 8. A photoelectric detection substrate, comprising: a plurality of reset control signal lines; a plurality of scan signal lines; a plurality of reference signal lines; a plurality of first initialization signal lines; a plurality of second initialization signal lines; a plurality of gate signal lines; and an array of pixel circuits; wherein each pixel circuit comprises: a charge storage circuit, a reset circuit, a photosensitive control circuit, and an output circuit; a first terminal and a second terminal of the charge storage circuit are electrically coupled to a first node and a second node, respectively; a first control terminal of the reset circuit is electrically coupled to a reset control signal line, a second control terminal of the reset circuit is be electrically coupled to a scan signal line; a first terminal, a second terminal and a third terminal of the reset circuit are electrically coupled to a reference signal line, a first initialization signal line, and a second initialization signal line, respectively; a fourth terminal, a fifth terminal, and a sixth terminal of the reset circuit are electrically coupled to the first node, a photodiode of the pixel circuit and the second node, respectively; a control terminal of the photosensitive control circuit is electrically coupled to a gate signal line; a first terminal, a second terminal and a third terminal of the photosensitive control circuit are electrically coupled to the photodiode, the first node and the second node, respectively; a first control terminal of the output circuit is electrically

Assignees

Inventors

Classifications

  • Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

  • applied to dark current · CPC title

  • H04N25/77Primary

    Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

  • H04N25/76Primary

    Addressed sensors, e.g. MOS or CMOS sensors · CPC title

  • Integration of the drivers onto the display substrate · CPC title

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Frequently asked questions

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What does patent US11636800B2 cover?
A pixel circuit includes: a charge storage circuit with first and second terminals thereof electrically coupled to first and second nodes, respectively; a reset circuit with first, second and third control terminals thereof electrically coupled to a reference signal line, a first initialization signal line, and a second initialization signal line, respectively, with fourth, fifth and sixth term…
Who is the assignee on this patent?
Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification H04N25/77. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 25 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).