Performance tuning of a hardware description language simulator

Patent metadata

Field	Value
Publication number	US-11636244-B1
Application number	US-202117490897-A
Country	US
Kind code	B1
Filing date	Sep 30, 2021
Priority date	Sep 30, 2020
Publication date	Apr 25, 2023
Grant date	Apr 25, 2023

Abstract

Some aspects of this disclosure are directed automated performance tuning of a hardware description language (HDL) simulation system. For example, some aspects of this disclosure relate to a method, including generating, by a first subsystem optimizer, a plurality of recommendations corresponding to a first subsystem of a hardware description language (HDL) simulation system. The plurality of recommendations are generated by the first subsystem optimizer using one or more optimization applications. The method further includes generating, by the first subsystem optimizer, a first aggregate recommendation by combining the plurality of recommendations corresponding to the first subsystem of the HDL simulation system. The method further includes updating a configuration of the first subsystem of the HDL simulation system based on the first aggregate recommendation, wherein the HDL simulation system is configured to simulate a circuit design using the updated configuration during execution of the first subsystem.

First claim

What is claimed is:

1. A method comprising:
generating, by a first subsystem optimizer, a plurality of recommendations corresponding to a first subsystem of a hardware description language (HDL) simulation system, wherein the plurality of recommendations are generated by the first subsystem optimizer using one or more optimization applications;
generating, by the first subsystem optimizer, a first aggregate recommendation by combining the plurality of recommendations corresponding to the first subsystem of the HDL simulation system; and
updating a configuration of the first subsystem of the HDL simulation system based on the first aggregate recommendation, wherein the HDL simulation system is configured to simulate a circuit design using the updated configuration during execution of the first subsystem.

2. The method of claim 1 , further comprising:
generating, by a second subsystem optimizer, a second aggregate recommendation by combining a plurality of recommendations corresponding to a second subsystem, wherein the plurality recommendations corresponding to the second subsystem are generated by the second subsystem optimizer using one or more optimization applications; and
combining, using a gating model, the first aggregate recommendation, the second recommendation, and a user input to generate a gating-mixture recommendation,
wherein updating the configuration of the first subsystem of the HDL simulation system comprises updating a configuration of the HDL simulation system based on the gating-mixture recommendation.

3. The method of claim 2 , wherein the combining is performed by the gated model using a random forest machine learning process.

4. The method of claim 1 , wherein an optimization application of the one or more optimization applications is based on a weak learner process.

5. The method of claim 1 , wherein an optimization application of the one or more optimization applications is based on a machine learning process.

6. The method of claim 1 , wherein an optimization application of the one or more optimization applications is based on a rule-based model.

7. The method of claim 1 , wherein the one or more recommendations corresponding to the first subsystem are combined using a weighted averaging.

8. The method of claim 1 , wherein the one or more recommendations are generated based on data related to one or more of test-bench constructs, design constructs, coverage constructs, assertion constructs, low power constructs, compile statistics, runtime statistics, switches, profiles, and simulator heuristics.

9. The method of claim 1 wherein the updated configuration comprises a specified set of computing resources for the HDL simulation system.

10. A system comprising:
a memory storing instructions; and
a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to:
generate a plurality of recommendations corresponding to a first subsystem of a hardware description language (HDL) simulation system using one or more optimization applications;
generate a first aggregate recommendation by combining the plurality of recommendations corresponding to the first subsystem of the HDL simulation system; and
update a configuration of the first subsystem of the HDL simulation system based on the first aggregate recommendation, wherein the HDL simulation system is configured to simulate a circuit design using the updated configuration during execution of the first subsystem.

11. The system of claim 10 , wherein the instructions when executed further cause the processor to:
generate a second aggregate recommendation by combining a plurality of recommendations corresponding to a second subsystem, wherein the plurality of recommendations corresponding to the second subsystem are generated using one or more optimization applications; and
combine the first aggregate recommendation, the second recommendation, and a user input to generate a gating-mixture recommendation,
wherein updating the configuration of the first subsystem of the HDL simulation system comprises updating a configuration of the HDL simulation system based on the gating-mixture recommendation.

12. The system of claim 11 , wherein the gated model uses a random forest machine learning process.

13. The system of claim 10 , wherein an optimization application of the one or more optimization applications is based on a weak learner process.

14. The system of claim 10 , wherein the one or more recommendations corresponding to the first subsystem are combined using a weighted averaging.

15. The system of claim 10 wherein the updated configuration comprises a specified set of computing resources for the HDL simulation system.

16. A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:
generate a plurality of recommendations corresponding to a first subsystem of a hardware description language (HDL) simulation system, wherein the plurality of recommendations are generated using one or more optimization applications;
generate a first aggregate recommendation by combining the plurality of recommendations corresponding to the first subsystem of the HDL simulation system; and
update a configuration of the first subsystem of the HDL simulation system based on the first aggregate recommendation, wherein the HDL simulation system is configured to simulate a circuit design using the updated configuration during execution of the first subsystem.

17. The non-transitory computer readable medium of claim 16 , the instructions when executed by a processor, further cause the processor to:
generate a second aggregate recommendation by combining a plurality of recommendations corresponding to a second subsystem, wherein the plurality of recommendations corresponding to the second subsystem are generated using one or more optimization applications; and
combine the first aggregate recommendation, the second recommendation, and a user input to generate a gating-mixture recommendation,
wherein updating the configuration of the first subsystem of the HDL simulation system comprises updating a configuration of the HDL simulation system based on the gating-mixture recommendation.

18. The non-transitory computer readable medium of claim 17 , wherein the gated model uses a random forest machine learning process.

19. The non-transitory computer readable medium of claim 16 , wherein an optimization application of the one or more optimization applications is based on a weak learner process.

Assignees

• Synopsys Inc

Inventors

• Gopalan Badri Prasad
• Cardozo Melvin
• Puthiya-Purayil Deepesh
• Doppalapudi Vamsi Krishna
• Chatterjee Trinanjan
• Wang Yichun

Classifications

• G06F30/3308 Primary

  using simulation · CPC title

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F30/27

  using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title