Processing metadata, policies, and composite tags

US11635960B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11635960-B2
Application numberUS-202016905680-A
CountryUS
Kind codeB2
Filing dateJun 18, 2020
Priority dateDec 17, 2015
Publication dateApr 25, 2023
Grant dateApr 25, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

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A method includes receiving, for metadata processing, a current instruction with associated metadata tags. The metadata processing is performed in a metadata processing domain isolated from a code execution domain including the current instruction. Each respective associated metadata tag represents a respective policy of the composite policy. For each respective metadata tag, the method includes determining, in the metadata processing domain and in accordance with the metadata tag and the current instruction, whether a rule exists for the current instruction in a rules cache. The rules cache may include rules on metadata used by the metadata processing to define allowed instructions. The determination of whether a rule exists results in a respective output, which may include generating a new rule and inserting the new rule in the rules cache. Control Status Registers, and associated tags, may be used to accomplish the metadata processing.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method of digital processor processing instructions comprising: in a system comprising a code execution domain and a metadata processing domain, the code execution domain is separated and isolated from the metadata processing domain by (i) preventing instructions of executing code from reading or writing metadata tags or rules to/from one or more control status registers based upon a protection level of the executing code, (ii) communicating information from the metadata processing domain to the code execution domain using one or more control status registers, wherein access to the one or more control status registers is permitted based upon a current mode and minimum privilege level of the one or more control status registers and a determined privilege level of the instructions, and (iii) communicating information from the code execution domain to the metadata processing domain using the one or more control status registers, receiving, for metadata processing, a current instruction with a plurality of associated metadata tags, the metadata processing being performed in the metadata processing domain isolated from the code execution domain that includes the current instruction, each respective associated metadata tag representing a respective policy of a composite policy, the plurality of associated metadata tags further including pointers to tags of a component policy of the composite policy; for each respective metadata tag of the plurality of associated metadata tags, determining, in the metadata processing domain and in accordance with the metadata tag and the current instruction, whether a rule exists in a rules cache for the current instruction, the rules cache including rules on metadata used by the metadata processing to define allowed instructions, each determination of whether a rule exists resulting in a respective output; responsive to determining no rule exists in the rules cache for the current instruction, performing rule cache miss processing in the metadata processing domain including determining whether execution of the current instruction is one of allowed and disallowed; responsive to determining the current instruction is allowed to be executed in the code execution domain, generating a new rule for the current instruction and, responsive to writing to a register in the metadata processing domain, inserting the new rule into the rules cache; wherein first metadata used to select the rule for the current instruction is stored in a first portion of a plurality of control status registers used by the metadata processing, and wherein the first portion of the plurality of control status registers is atomically read based upon a determined privilege level of the current instruction and used to communicate a plurality of metadata tags for the current instruction to the metadata processing domain, wherein the plurality of metadata tags is used as data in the metadata processing domain. 2. The method of claim 1 , further comprising: generating a composite result tag by combining the respective outputs into a single metadata tag representing the composite policy that includes each respective policy; and inserting a new rule into the rules cache, the new rule comprising (i) the current instruction and associated metadata tags, and (ii) the composite result tag. 3. The method of claim 1 , wherein determining whether a rule exists in a rules cache further includes: for each metadata tag, determining whether a rule exists in a first level cache; when it is determined that no rule is present in the first level cache, determining whether a rule exists in a second level cache. 4. The method of claim 1 , wherein the rules cache is at least one of a Unified Component Policy (UCP) cache, composite set of tag (CTAG) cache, or data cache. 5. The method of claim 1 , wherein: a composite set of tag (CTAG) cache stores composite results based on combinations of metadata tag values, and generating the composite result tag includes combining the respective outputs into a single metadata tag by looking up a combination of the respective outputs in the CTAG cache. 6. The method of claim 1 , wherein the first portion of the plurality of control status registers comprises an Opgrp tag that denotes a particular opgroup that includes a current instruction. 7. The method of claim 1 , wherein the first portion of the plurality of control status registers comprises a PCtag tag that is associated with a program counter. 8. The method of claim 1 , wherein the first portion of the plurality of control status registers comprises CItag tag that is associated with the current instruction. 9. The method of claim 1 , wherein the first portion of the plurality of control status registers comprises an OP1tag that is associated with an RS1 register input to the current instruction. 10. The method of claim 1 , wherein the first portion of the plurality of control status registers comprises an OP2tag that is associated with an RS2 register input to the current instruction. 11. The method of claim 1 , wherein the first portion of the plurality of control status registers comprises an OP3tag that is associated with an RS3 register input to the current instruction. 12. The method of claim 1 , wherein the first portion of the plurality of control status registers comprises an Mtag tag that is associated with a memory input to a current instruction or a memory target of the current instruction. 13. The method of claim 1 , wherein the first portion of the plurality of control status registers comprises a funct12 tag associated with extended opcode bits of the current instruction. 14. The method of claim 1 , wherein the first portion of the plurality of control status registers comprises a subinstr tag that identifies which instruction in a word is the current instruction being operated upon.

Assignees

Inventors

Classifications

  • G06F21/52Primary

    during program execution, e.g. stack integrity {; Preventing unwanted data erasure; Buffer overflow} · CPC title

  • Security improvement · CPC title

  • comprising a single central processing unit · CPC title

  • Special purpose registers · CPC title

  • Encrypted data · CPC title

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What does patent US11635960B2 cover?
A method includes receiving, for metadata processing, a current instruction with associated metadata tags. The metadata processing is performed in a metadata processing domain isolated from a code execution domain including the current instruction. Each respective associated metadata tag represents a respective policy of the composite policy. For each respective metadata tag, the method include…
Who is the assignee on this patent?
Charles Stark Draper Laboratory Inc
What technology area does this patent fall under?
Primary CPC classification G06F21/52. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Apr 25 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).