Multi-rate digital sensor synchronization

Patent metadata

Field	Value
Publication number	US-11635311-B2
Application number	US-201916421455-A
Country	US
Kind code	B2
Filing date	May 23, 2019
Priority date	May 25, 2018
Publication date	Apr 25, 2023
Grant date	Apr 25, 2023

Abstract

A system and method for multi-rate synchronization of a digital sensor that provides a digital sensor output signal and a processor arrangement that processes the digital sensor output signal according to a processing algorithm and that provides a processor output signal, including operating the digital sensor to provide the digital sensor output signal with a first sample rate, and operating the processor arrangement to provide a processor output signal with a second sample rate. The second sample rate is an integer multiple of the first sample rate.

First claim

The invention claimed is:

1. A method for multi-rate synchronization of a digital sensor that provides a digital sensor output signal and a processor arrangement that processes the digital sensor output signal according to a processing algorithm and that provides a processor output signal, the method comprising the steps of:
operating the digital sensor to provide the digital sensor output signal with a first sample rate;
in a processor arrangement that has a main processor and a host processor, the processor arrangement is separate from a transceiver of the digital sensor, the main processor has a second sample rate that is an integer multiple of the first sample rate;
generating a trigger signal in the host processor at the first sample rate, the trigger signal triggers polling of the digital sensor output signal when a new sample of the digital sensor output signal is available;
forwarding the trigger signal to the digital sensor to synchronize polling of the digital sensor output signal at the first sample rate;
forwarding the trigger signal to the main processor;
in response to receiving the trigger signal from the host processor, the main processor samples the digital sensor output signal using both the first and the second sample rates;
synchronizing, in the main processor, the digital sensor output signal of the first sample rate with the digital signal sensor output signal of the second sample rate thereby generating a processor output signal at the second sample rate; and
outputting the processor output signal at the second sample rate.

2. The method of claim 1 , further comprising the step of:
delaying the trigger signal that triggers processing of the digital sensor output signal when a new sample of the digital sensor output signal is available.

3. The method of claim 1 , wherein the digital sensor output signal is a data stream including data from the digital sensor, the method further comprising the step of decoding the data of the data stream from the digital sensor.

4. The method of claim 3 , wherein the data from the digital sensor are of a predefined data type and the step of decoding is performed immediately upon receipt of the data stream from the digital sensor by the processor arrangement.

5. The method of claim 1 , further comprising the step of compensating delays occurring before processing of the digital sensor output signal according to the algorithm.

6. The method of claim 5 , wherein the step of compensating the delays is based on a fixed compensation scheme.

7. The method of claim 1 , further comprising the step of interpolating the processor output signal using at least one of sampling and low-pass filtering of the processor output signal.

8. A system for multi-rate synchronization of a digital sensor that is configured to provide a digital sensor output signal and a processor arrangement that is configured to process the digital sensor output signal according to a processing algorithm and to provide a processor output signal, wherein:
the digital sensor is further configured to provide the digital sensor output signal with a first sample rate;
the processor arrangement is separate from a transceiver of the digital signal processor, the processor arrangement has a main processor and a host processor, the main processor has a second sample rate that is an integer multiple of the first sample rate;
a trigger signal is generated in the host processor of the processor arrangement when a new sample of the digital sensor output signal is available;
the trigger signal is forwarded to the digital sensor to trigger polling of the digital sensor output signal;
the trigger signal is forwarded to the main processor to trigger sampling of the digital sensor output signal using the first and second sample rates;
the main processor of the processor arrangement synchronizes the digital sensor output signal using both the first and the second sample rates thereby generating a processor output signal; and
the processor output signal is output by the main processor using the second sample rate.

9. The system of claim 8 , wherein the processor arrangement is further configured to:
delay the trigger signal that triggers processing of the digital sensor output signal when a new sample of the digital sensor output signal is available.

10. The system of claim 8 , wherein the digital sensor output signal is a data stream including data from the digital sensor, the method further comprising decoding the data of the data stream from the digital sensor.

11. The system of claim 10 , wherein the data from the digital sensor are of a predefined data type and decoding is performed immediately upon receipt of the data stream from the digital sensor by the processor arrangement.

12. The system of claim 8 , wherein the processor arrangement is further configured to compensate delays occurring before processing of the digital sensor output signal according to the algorithm.

13. The system of claim 12 , wherein compensating the delays is based on a fixed compensation scheme.

14. The system of claim 8 , wherein the processor arrangement is further configured to interpolate the processor output signal, interpolating the processor output signal using at least one of sampling and low-pass filtering of the processor output signal.

Assignees

• Harman Becker Automotive Systems Gmbh

Inventors

• Cao Yuliu
• Zollner Juergen
• Lorenz Franz
• Gao Bin
• Chen Shiyu
• Zhou Tingting
• Lee Alex

Classifications

• H04Q9/04 Primary

  Arrangements for synchronous operation · CPC title

• H04L7/0008 Primary

  Synchronisation information channels, e.g. clock distribution lines · CPC title

• G01D18/00 Primary

  Testing or calibrating apparatus or arrangements provided for in groups G01D1/00 - G01D15/00 · CPC title

• G01D21/02

  Measuring two or more variables by means not covered by a single other subclass · CPC title