Near-optimal transition encoding codes

Patent metadata

Field	Value
Publication number	US-11632127-B2
Application number	US-202117506481-A
Country	US
Kind code	B2
Filing date	Oct 20, 2021
Priority date	Aug 4, 2021
Publication date	Apr 18, 2023
Grant date	Apr 18, 2023

Abstract

A method of encoding input data includes dividing the input data into a plurality of data packets, an input packet of the plurality of data packets including a plurality of digits in a first base system, base-converting the input packet from the first base system to generate a base-converted packet including a plurality of converted digits in a second base system, the second base system having a base value lower than that of the first base system, and incrementing the converted digits to generate a coded packet for transmission through a communication channel.

First claim

What is claimed is:

1. A method of encoding input data, the method comprising:
dividing the input data into a plurality of data packets, an input packet of the plurality of data packets comprising a plurality of digits in a first base system;
base-converting the input packet from the first base system to generate a base-converted packet comprising a plurality of converted digits in a second base system, the second base system having a base value lower than that of the first base system; and
incrementing the converted digits to generate a coded packet for transmission through a communication channel.

2. The method of claim 1 , wherein a number of the plurality of converted digits in the base-converted packet is one more than a number of the plurality of digits in the input packet.

3. The method of claim 1 , wherein the incrementing the converted digits comprises:
incrementing each of the converted digits by one to generate coded digits, the coded packet comprising the coded digits.

4. The method of claim 1 , wherein the coded packet has a run-length less than or equal to a set run-length value.

5. The method of claim 1 , wherein the input packet comprises N digits, each of the N digits comprising q bits,
wherein the first base system is a base 2 q system, and the second base system is a base 2 q −2 system, and
wherein the coded packet has a run-length less than or equal to 2q−2.

6. The method of claim 1 , wherein the input packet comprises N digits, each of the N digits comprising q bits, and
wherein the first base system is a base 2 q system, and the second base system is a base 2 q −3 or less system.

7. The method of claim 1 , wherein the input packet is an N-digit base-2 q number expressed as
X =[ x 1 x 2 . . . x N ] 2 q ,
wherein each of digits x 1 , x 2 , . . . x N has a value from 0 to 2 q −1,
wherein the base-converted packet is an (N+1)-digit base-(2 q −2) number expressed as
X =[ y 0 y 1 y 2 . . . y N ] 2 q −2 , and

wherein each of the plurality of digits y 1 , . . . y N has a value from 0 to 2 q −3.

8. The method of claim 7 , wherein an overhead digit y 0 has a value from 0 to 2 q −3, and
wherein values N and q have a relationship expressed as:
N<= 1/(log(2 q )/log(2 q −2)−1).

9. The method of claim 7 , wherein an overhead digit y 0 is a single binary bit, and
wherein values N and q have a relationship expressed as:
N <=log 2/(log(2 q )−log(2 q −2)).

10. The method of claim 7 , wherein the coded packet is expressed as
X′={y 0 +1, y 1 +1, y 2 +1, . . . , y N +1}, and
wherein each of coded digits y 0 +1 . . . y N +1 do not include all zeros or all ones.

11. The method of claim 1 , wherein the base-converting the input packet comprises an iterative process comprising only shift, addition, and subtraction operations.

12. The method of claim 1 , wherein the coded packet comprises at least one bit transition.

13. The method of claim 1 , further comprising:
transmitting transmission data to a receiver through the communication channel, the transmission data comprising the coded packet.

14. A transition encoder for encoding input data, the transition encoder comprising:
a processor; and
a processor memory local to the processor, wherein the processor memory has stored thereon instructions that, when executed by the processor, cause the processor to perform:
dividing the input data into a plurality of data packets, an input packet of the plurality of data packets comprising a plurality of digits in a first base system;
base-converting the input packet from the first base system to generate a base-converted packet comprising a plurality of converted digits in a second base system, the second base system having a base value lower than that of the first base system; and
incrementing the converted digits to generate a coded packet for transmission through a communication channel.

15. A method of decoding transmission data, the method comprising:
dividing the transmission data into a plurality of coded packets, a coded packet of the plurality of coded packets comprising a plurality of coded digits in a first base system;
decrementing the plurality of coded digits to generate a converted packet; and
base-converting the converted packet from the first base system to generate a decoded packet comprising a plurality of decoded digits in a second base system, the second base system having a base value greater than that of the first base system.

16. The method of claim 15 , wherein a number of the plurality of coded digits in the coded packet is one more than a number of the plurality of decoded digits in the decoded packet.

17. The method of claim 15 , wherein the decrementing the coded digits comprises:
decrementing each of the coded digits by one to generate converted digits, the converted packet comprising the converted digits.

18. The method of claim 15 , wherein each of the coded packets has a run-length less than or equal to a set run-length value.

19. The method of claim 15 , further comprising:
receiving the transmission data from a transmitter through a communication channel.

20. A transition decoder for decoding a transmission data, the transition decoder comprising:
a processor; and
a processor memory local to the processor, wherein the processor memory has stored thereon instructions that, when executed by the processor, cause the processor to perform:
dividing the transmission data into a plurality of coded packets, a coded packet of the plurality of coded packets comprising a plurality of coded digits in a first base system;
decrementing the plurality of coded digits to generate a converted packet; and
base-converting the converted packet from the first base system to generate a decoded packet comprising a plurality of decoded digits in a second base system, the second base system having a base value greater than that of the first base system.

Assignees

• Samsung Display Co Ltd

Inventors

• Abbasfar Aliazam
• Amirkhany Amir

Classifications

• H03M7/46 Primary

  Conversion to or from run-length codes, i.e. by representing the number of consecutive digits, or groups of digits, of the same kind by a code word and a digit indicative of that kind · CPC title

• H03M7/3064

  Segmenting · CPC title

• H04L25/4908 Primary

  using mBnB codes · CPC title

• H04L25/4915

  using pattern inversion or substitution (H04L25/4908 takes precedence) · CPC title

• H03M7/6011

  Encoder aspects · CPC title